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Increasing on-chip power densities with aggressive technology scaling has led to a low-power FPGA fabric with dual supply voltages. Such low-power techniques coupled with the heterogeneity of components on a FPGA have led to non-uniform aging of components due to temperature and voltage dependent failure mechanisms. In this paper, we present techniques in placement and routing stages of the design...
The design of power grid network is critical in scaled technologies for reliable operation of a circuit. This paper presents novel CAD techniques for mitigating IR-drops in FPGAs. Placement and routing techniques are developed in the paper for improving the voltage profile of the power grid network. The proposed techniques not only improve the minimum voltage at any node in the FPGA power grid, but...
A new application-independent approach for evaluating the fault tolerance of field-programmable gate-array (FPGA) interconnect structures is presented. Signal routing in the presence of faulty resources at switch block and FPGA levels is analyzed; this problem is directly related to the fault tolerance of FPGA interconnects for testing and reconfiguration at manufacturing and run-time applications...
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