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This paper proposes the utilization of VHDL (Very High Speed Integrated Circuit plus Hardware Description Language) for developing a novel Distribution Management System (DMS) and control architecture for electrical distribution systems. Developed DMS and control architecture utilizes a FPGA (Field Programmable Gate Array) device allowing electrical feeder control. This DMS and control architecture...
Partial Reconfiguration is one of the most attractive features of FPGAs. This feature provides new computing possibilities, such as the reduction of the total area required in a FPGA by means of functioning overlapping, or the modification of the design after its deployment, where a complete configuration is not needed. However, the design of partially reconfigurable systems is still a complex task...
For secure data transmission cryptographic algorithms are used for many applications. This paper introduces optimized hardware implementation of area and speed improvement for the block cipher Advanced Encryption Standard (AES-128) using Field Programmable Graphic Array (FPGA). As AES has four transformations among them sub-byte and mix-column transformation are key challenges to implement in terms...
The Distributed Network Protocol (DNP) is the communication protocol standard for Electric Power Systems (EPS) and it is a promising communication standard for the Electric Intelligent Devices (IEDs) found in Smart Grids. This paper presents a hardware implementation of the Data Li nk layer specified in version 3.3 of DNP (DNP3). A 100 Mbps Ethernet-based Distributed Network Protocol has also been...
In this paper, hardware implementation of the IEEE 802.22 Interleaver is presented. The key challenge in implementing the interleaver is its address generator unit as other units implementation is straightforward. Two fully-combinational and combinational-sequential architectures of the address generator are designed using and synthesized VHDL and compared in terms of area, timing, and power. Simulation...
Advanced Encryption Standard (AES), a Federal Information Processing Standard (FIPS), is an approved cryptographic algorithm that can be used to protect electronic data. The AES can be programmed in software or built with pure hardware. However Field Programmable Gate Arrays (FPGAs) offer a quicker and more customizable solution. This paper presents the AES algorithm with regard to FPGA and the Very...
In this paper is proposed and analyzed a digital hysteresis modulation using a FPGA (field programmable gate array) device and VHDL (hardware description language), applied at a hybrid three-phase rectifier with almost unitary input power factor, composed by parallel SEPIC controlled single-phase rectifiers connected to each leg of a standard 6-pulses uncontrolled diode rectifier. The digital control...
In this paper is proposed and analyzed a digital hysteresis modulation using a FPGA (Field Programmable Gate Array) device and VHDL (Hardware Description Language), applied at a hybrid three-phase rectifier with almost unitary input power factor, composed by parallel SEPIC controlled single-phase rectifiers connected to each leg of a standard 6-pulses uncontrolled diode rectifier. The digital control...
It has become clear that the current generation of cryptographic hashing algorithms are insufficient to meet future needs. Hash functions are among the most widespread cryptographic primitives, and are currently used in multiple cryptographic schemes and security protocols such as IPSec and SSL. In this paper, a hardware implementation of the newly proposed draft hash standard SHA-512 achieves high...
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