The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
This paper proposes HSTL based energy efficient design of frame buffer for a digital image processor. Our aim is to make energy efficient frame buffer design and for that reason we are using different types of HSTL IO standards. This design is implemented on both Virtex-6 FPGA and Airtex-7 FPGA and compared the power dissipation. It is observed that at 1GHz operating frequency, there is maximum IO...
The paper presents a prototype of Image Acquisition Module (IAM) dedicated for plasma monitoring. The complete frame grabber together with camera controller, timing and communication interfaces is fitted in one Advanced Mezzanine Card (AMC) to maintain compatibility with the Micro Telecommunications Computing Architecture (<TCA) standard.
In this paper, a design of a dual symbol processor for arithmetic coder architecture implemented on FPGA is proposed. Usually, the regular operation of the MQ-Coder is sequential, which can process only one symbol at a time. However, the bit-plane coding can generate more than one symbol per clock cycle. Consequently, the coding speed will be limited and bottlenecked at the interface between the output...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.