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The novel implantable stimulus driver for epileptic seizure suppression with low power design and adaptive loading consideration was proposed in this work. The stimulus driver consisted of the output stage, charge pump system, and adaptor can constantly provide 40-μA output stimulus currents, as the electrode impedance varies within 10~300 kΩ. The performances of this design have been successfully...
Large supply bouncing due to the fast switching current and parasitic inductance of the supply rail may cause reliability and electromagnetic interference (EMI) problems, especially for ICs with the pulse-width modulation (PWM) technique, such as switching DC-DC converters. In this paper, a new slew-rate controlled (SRC) output stage is proposed to appropriately increase the rise and fall times of...
This paper presents a highly efficient switched capacitor (SC) DC-DC converter, which is implemented in a 65nm low power CMOS process to enable SoC integration. The converter supplies a nominal output current of 30mA with an efficiency of 95%. The buck converter operates with a constant input voltage of 1.83V and produces an output voltage of 1.2V. The charge is transported in two phases from the...
This paper describes CMOS interface circuits in 350nm 3.3V/5.0V TSMC process for memristor crossbar array. These circuits are applicable for non-volatile resistive memories. The architecture is targeted for low power and high speed applications. We have demonstrated sense amplifiers for reading the state of a memristor bit. Voltage divider and transimpedence amplifier is used for DC sensing while...
A digital-to-analog converter with current-steering architecture suitable for CMOS 0.18µm process is designed. An 4+4 + 4 segmented architecture is presented, and the trade-off between area and performance is considered. The circuit has been simulated and a desirable result is achieved.
This paper presents a simple, ultra-compact and isolated gate driver system used to drive power switches. Using two legs of a CMOS inverter, a high frequency transformer and two zener diodes connected with the gate of power switch, this driver provides an optimal gate driver waveform with a high gate voltage to switch on the transistor, and a negative bias gate voltage during OFF state. In the paper,...
For cellular handset ICs, integrating the power management unit (PMU) in the same chip as the baseband and the radio is critical for footprint and cost reduction, however, it presents unique challenges in terms of device reliability, bill of materials (BOM) and PMU performance. In this paper, a PMU integrated as part of a GSM/EDGE chip in a 65nm deep-Nwell CMOS process, comprising a battery charger,...
A 2.4 GHz outphasing power amplifier (PA) is implemented in a 32 nm CMOS process. An inverter-based class-D PA topology is utilized to obtain low output impedance and good linearity in the outphasing system. MOS switch non-idealities, such as finite on-resistance and finite rise and fall times are analyzed for their impact on outphasing linearity and efficiency. Outphasing combining is performed via...
This paper presents an amplitude shift keying (ASK) transmitter for high-quality imaging in ingestible capsule endoscopy application. A carrier frequency of 900MHz is generated by a complementary LC voltage-controlled oscillator, and directly modulated with a digital baseband ASK signal by switching on and off a driver amplifier (DA). The modulated signal is amplified by the DA and transmitted through...
A 12-bit 800-MS/s DAC implemented in 90-nm CMOS is presented. The design uses three interleaved, pipelined, switched-capacitor cores followed by an open-loop output driver. The driver is linearized using digital predistortion. Measured SFDR is greater than 58 dB for signal frequencies below 200 MHz, and greater than 53 dB for signal frequencies below 400 MHz, all with output swings as large as 2.9...
A novel frequency hopping technique is proposed to increase the efficiency in a switched-capacitor LED driver, based on analyzing the dependence of power loss on switching frequency. LEDs' load current is featured uniquely by jumping periodically from a constant value (20mA) to zero for dimming function. Developed on an improved VCO, the hopping technique makes the switching frequency vary discretely...
A novel 150V-BCD technology by using 14um thick epitaxy based on 0.35um standard CMOS process has been developed for LCD backlighting application. In the whole process with 24 steps, HV circuit block, including VDNMOS and LDPMOS with double resurf principle, and LV block are integrated together. Advanced deep trench isolation (DTI) technology with the breakdown voltage above 150V is firstly in place...
It is critically important to maintain charge balance in neural stimulation, employing biphasic current pulses. Any mismatch in biphasic current pulses will result in charge imbalance, possibly leading to tissue damage. In this paper, we propose an implantable stimulator for bipolar stimulation to minimize the mismatch of biphasic current pulses, without dc blocking capacitors or charge balancing...
In this paper, a one-dimensional linear gradient error compensation in current-steering is implemented in the digital-to-analog (DAC) arrays. A new approach of current cells optimal switching sequences that have a minimum variance of error is proposed. The proposed DAC adapts a 4-4-2 segmentation architecture to achieve high speed application. The simulation results show that the proposed design can...
A 5-bit 2GS/s current-steering D/A converter for ultra-wideband (UWB) transceivers is presented in this paper. It is based on a full-binary weighted architecture and achieves better than 10-bit static linearity without calibration. The DAC occupies 0.5mm × 0.75mm in a standard 90nm CMOS technology. A spurious-free dynamic range (SFDR) of more than 30dB has been measured over the complete Nyquist interval...
This paper describes the design and simulation of a temperature-insensitive gate-controlled weighted current digital-to-analog converter (DAC). The DAC design includes CMOS drivers to switch the gates of a set of binary-weighted PMOS current sources. Temperature-insensitive operation is achieved by biasing the PMOS current sources at their zero temperature coefficient (ZTC) voltage. The proposed DAC...
This paper introduces a novel current output stage with a Digital assistant circuit, which can obtain high speed performance. The output current stage in this paper is used in a switching driving circuit. The principle of this proposed circuit is different with the conventional structure. The added Digital assistant circuit includes a charge and discharge block, a keep block. Depended on simple digital...
This paper introduces the design of High-Voltage CMOS drivers for Electrostatic MEMS switches. In order to perform online diagnosis, the proposed architecture implements a dedicated circuitry that can detect the pull-in event. This way, stuck or broken switches are identified during operation. The pull-in event corresponds to a rapid change in the actuation capacitance thus producing a current peak...
A novel high-speed and low-power negative level shifter suitable for low voltage applications is presented. To reduce the switching delay and leakage current, a novel bootstrapping technique is designed for the level shifter. Furthermore, a pull-down driver is proposed to have high driving capability under different operation modes. The circuit has been designed in 130 nm 1.5 V/5 V triple-well CMOS...
We present a process variation tolerance technique for current sensing on-chip links. Process variation affects the signal integrity of a current sensing receiver. As the amount of worst-case current variation is increasing in sub-100 nm technologies, the conventional worst-case process variation assumption has a high power consumption cost. We propose adjusting currents at every power start-up of...
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