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In this paper, a novel modified 4T Content addressable memory (CAM) cell based Master-Slave Match Line (MSML) design for memory architectures is proposed. In memory architectures, match lines (MLs) and search lines (SLs) are main source of power consumption. The Proposed Modified 4T CAM cell based MSML design which reduces delay by 74%–95% with increases total power consumption and area compared with...
This paper analyzes the benefits of using half-unit-biased (HUB) formats to implement floating-point (FP) arithmetic under a round-to-nearest mode from a quantitative point of view. Using the HUB formats to represent numbers allows the removal of the rounding logic of arithmetic units, including sticky-bit computation. This is shown for FP adders, multipliers, and converters. Experimental analysis...
This work addresses an all digitally-controlled oscillator (DCO) design with three newly proposed hysteresis delay cells (HDC). According to circuit topologies, the three HDCs are defined as on-off, cascaded, and nested HDCs that provide different propagation delay. These HDCs comprise architecture, a power-of-two delay stage DCO (P2DCO), that every delay stage provides half delay than the previous...
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