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The paper is dedicated to hardware accelerators for data sorting using tree-based recursive algorithms. Since recursive calls are not directly supported by hardware description languages, they are implemented using the model of a hierarchical finite state machine. The paper presents new results in: 1) computational models and hardware architectures; 2) optimization and parallel execution of recursive...
The use of synthesizable reconfigurable IP cores has increasingly become a trend in System on Chip (SoC) designs because of their flexibility and powerful functionality. The market introduction of multi-featured platform FPGAs equipped with embedded memory and processor blocks has further expanded the possibility of utilizing dynamic reconfiguration to improve overall system adaptability to meet varying...
The paper presents new results in the hardware implementation and optimization of recursive sequential and parallel algorithms using the known and a new model of a hierarchical finite state machine. Applicability and advantages of the proposed methods are confirmed through numerous examples of the designed hardware circuits that have been analyzed and compared. The results of experiments and FPGA-based...
This paper explores the advantages of adding an MMX extension to the MicroBlaze (MB) soft processor,through its FSL ports. The implemented MMX unit is described in detail, were emphasis has been done in parallelizing the instruction execution. The propagation delays and FPGA resources consumed obtained for the different blocks during the synthesis phase for a Virtex-II target device are also shown...
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