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In this paper we present an example of a DISPLAY-CTRL IP component verification in an SCE-MI based emulation platform. The basic parts of this platform are some transactors. Their task is communication between the testbench written in the high level language SystemC (software side) and the IP component, placing in FPGA on an emulation board (hardware side) through an SCE-MI infrastructure. Using the...
Solving systems of linear and nonlinear equations is of fundamental importance at the basic level of a vast array of science and engineering applications. As these applications become more computationally complex, the need for low cost, high performance computing methods increases. This paper discusses different approaches to reduce computation time to solve linear equations by using a hardware/software...
This paper presents the performance analysis hardware/software co-design of iterative methods for solving linear systems in terms of speed, iteration and toleration. Three iterative methods, Jacobi, Gauss-Seidel (GS) and conjugate gradient (CG), are implemented using Xilink EDK (embedded development kit). For comparison purposes, the same methods are also implemented in pure software using Xilink...
PTL (projection temporal logic) is a kind of temporal logic which can handle both sequential and parallel computation. In this paper, we proposed a formal approach of specification and verification of SOC using PTL. With this approach, PTL is used in high level design and hardware/software co-design for the formal specification and verification of a SOC system or its hardware/software parts. A simple...
This paper addresses problems associated with verification and FPGA prototyping platform preparation for the pre-silicon software development. Increasing the size of modern SoC makes traditional approach of mapping entire design into one FPGA unsuitable. Consequently, other more appropriate scheme must be found in order to achieve optimal results. One solution for the problem could be platforms with...
Embedded systems are a mixture of software running on a microprocessor and application-specific hardware. Hardware-software codesign requires an appropriate profiler to detect the functions that contribute to a large percentage of program execution. Software based profiling tools, such as the well-known GNU gprof profiler, integrates an extra code with the software program to be profiled causing a...
Hardware/software co-simulation integrates software simulation and hardware simulation simultaneously. HW/SW co-simulation platforms can facilitate debugging and verification for VLSI design. In this paper, two hardware/software co-simulation platforms are proposed. The first solution is a large-scale platform which supports complex VLSI co-simulation. The hardware part of design under test (DUT)...
Computing the irreducible and primitive polynomials under GF(3) is a computationally intensive task. A hardware implementation of this algorithm should prove to increase performance, reducing the time needed to perform the computation. Previous work explored the viability of a co-designed approach to this problem and this work continues addressing the problem by moving the entire algorithm into hardware...
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