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This paper presents design of a new stable 14T full power efficient adder circuit. The proposed circuit is designed based on Pass Transistor Logic (PTL) network using NMOS transistor only. The proposed circuit is simulated at layout level using Microwind EDA tools for 45nm technology in terms of power and voltage level at the sum and carry nodes. The proposed circuit performance is compared with a...
The continuous reduction of feature size and increase in chip density have made power becomes an important design parameter in today's deep submicron digital designs. Conversely, design engineers perform power estimation and optimization at every design stage to improve the performance and productivity of the design. During most synthesis process, synthesis tools prefer to use larger gates in the...
In this article, the main design tradeoffs in design of ultra-low-power (ULP) and robust digital systems will be discussed. Here, the goal is to explore the main tradeoffs among design parameters such as device sizes and supply voltage, and system parameters such as robustness and energy dissipation. This study provides the necessary basis for design optimization and comparing the conventional CMOS...
A general concern in VLSI design is power efficiency. It is indeed very obvious that battery operated equipment, such as handheld cellular phones, laptop computers etc. impose stringent limits on the acceptable power dissipation. The power dissipation of CMOS circuits is determined at different levels. On the system/architecture level, pipelining, replication, retiming, and bit-serial operation can...
In this work, a new design approach in implementing low-energy, high-performance 64-bit adder using dynamic feedthrough logic (DFTL) is introduced and analyzed. Design issues of using DFTL in several logic depth are analyzed in order to achieve the best optimal balance between performance and power consumption. A ldquotiming windowrdquo technique is also proposed to reduce the amount of excessive...
This paper presents a new study over logics circuit operation in subthreshold and threshold region. CMOS circuit model operation logic will make deep primary reference for this study. This new research presses low voltage features to circuit stated. By using profoundest results of the study, we will develop FFT processor designs as an example of digital wireless circuits. The FFT processor can operate...
Conventional programmable logic arrays (PLAs) implement both the AND and OR logic planes with dynamic NOR gates. They are fast, regular in structure and easy to program. However, they have high power dissipation and suffer from an inherent timing race that increases design effort, reduces circuit robustness in the presence of variations, and adversely impacts performance. In this paper, a PLA which...
While the CMOS analog circuits can be designed with the minimum-gate-length of the fabrication process in the alpha-power law MOSFET model, the length of a MOSFET gate has been chosen to be a larger scale than the minimum-gate-length in the conventional Shockleypsilas square model. In this paper, we describe a 6-b 100 MSPS CMOS current steering digital-to-analog converter (DAC) with the alpha-power...
A delay-locked loop of multi-band selector with wide-locking range and low power dissipation is presented. The architecture of the proposed delay-locked loop consists of phase frequency detector, charge pump, band selector, multi-control delay line, and start-up circuit. The multi-band selector is used to extend operation frequency of delay-locked loop by switching the multi-control delay line. The...
This paper describes a design flow for the circuit-level optimization of a technology. The concurrent exploration of device characteristics and library design choices leads to a more application-optimal technology. We illustrate the design flow by: 1) analyzing the impact of buffer cell design, and 2) by optimizing a 130 nm technology for low operational power.
3D contactless technology based on capacitive coupling represents a promising solution for high-speed and low power signaling in vertically integrated chips. AC coupled interconnects do not suffer from mechanical stress, and the parasitic load is much reduced when compared to standard DC solutions, such as wire bonding and micro bumps. Communication system based on wireless interconnection scheme...
Applying an aggressive policy to a traditional drowsy cache block management is investigated, where each cache line is allowed to remain in low leakage, low voltage state as long as it is idle. Only for write and read operations, the normal high voltage is applied to the cache line. There is no need for extra cycles or extra control signals to awake the drowsy cache cell, before accessing it. Thus,...
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