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A comparison of delay time (td) for n- and p-MOSFETs switches with silicon on sapphire (SOS), silicon on insulator (SOI) and bulk silicon structures is presented. Two step TCAD-SPICE simulation procedure was used to define td for the set of 3.0…0.25 um MOSFETs fabricated by the three mentioned technologies. It was shown that 0.5 um Peregrine UTSi SOS n- and p-MOSFET provided the td reduction of 220–240%...
Polymorphic gates can be considered as a new reconfigurable technology capable of integrating logic functions with sensing in a single compact structure. Polymorphic gates whose logic function can be controlled by the level of the power supply voltage (Vdd) represent a special class of polymorphic gates. A new polymorphic NAND/NOR gate controlled by Vdd is presented. This gate was fabricated and utilized...
While the CMOS analog circuits can be designed with the minimum-gate-length of the fabrication process in the alpha-power law MOSFET model, the length of a MOSFET gate has been chosen to be a larger scale than the minimum-gate-length in the conventional Shockleypsilas square model. In this paper, we describe a 6-b 100 MSPS CMOS current steering digital-to-analog converter (DAC) with the alpha-power...
Recent silicon process technology advancements have given chip designers integration capabilities never were possible before, and have led to a new wave of complex ASICs (applied specific integrated circuits). These advanced processes come with new challenges. This paper presents some of the challenges in deep submicron technologies, which require new design practices. We demonstrate some issues related...
This paper introduces a novel current sense amplifier (CSA) in sub-32nm fully depleted (FD) double-gate (DG) silicon-on-insulator (SOI) technology with planar independent self-aligned gates. A new architecture is proposed which takes advantage of the back gate in order to improve circuit properties. Compared to the reference circuit, the new architecture proves to be faster (21% sensing delay decrease),...
3D contactless technology based on capacitive coupling represents a promising solution for high-speed and low power signaling in vertically integrated chips. AC coupled interconnects do not suffer from mechanical stress, and the parasitic load is much reduced when compared to standard DC solutions, such as wire bonding and micro bumps. Communication system based on wireless interconnection scheme...
Design and characterization of a new generation of single-photon avalanche diodes (SPAD) array, manufactured by ST-Microelectronics in Catania, Italy, are presented. Device performances, investigated in several experimental conditions and here reported, demonstrate their suitability in many applications. SPADs are thin p-n junctions operating above the breakdown condition in Geiger mode at low voltage...
Sublinear signal propagation delay in VLSI circuits carries a far greater penalty in wire area than is commonly realized. Therefore, the global complexity of VLSI circuits is more layout dependent than previously thought. This effect will be truly pronounced in the emerging wafer scale integration technology. We establish lower bounds on the trade-off between sublinear signalling speed and layout...
Previous papers have shown that for any given n-input synchronous sequential machine there exists a circuit realization in which the circuit consists of a finite number of identical copies of one module and in which the modules are interconnected in a uniform manner. This paper shows that additionally the signal fan-in to every module and the signal fan-out from every module and from the input can...
It is generally recognized that asynchronous operation of logic networks offers specific advantages over synchronous operation controlled by a central clock when the network is subject to large or widely varying inter-module propagation delays. In this paper we characterize several previously described techniques for achieving asynchronous operation by a single model. Essential to the model is the...
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