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We present circuit design aspects of fully depleted extremely thin SOI (ETSOI) enabling 22 nm low-power CMOS and beyond, and demonstrate that all devices including analog, I/O, and passive devices can be fabricated in the thin silicon layer. Excellent device matching, gm/gds scaling to small gate length, good RF performance, and absence of history effect are the main features of the ETSOI technology.
Systematic study on hole mobility in gate-all-around (GAA) multiple Si nanowire (NW) pFETs on (110) SOI is presented for the first time. [110]-NWs show high mobility, 2.4times enhancement over universal (100) mobility, even in high Ninv region and in narrow (25 nm) NWs. Furthermore, effects of uniaxial tensile stress are also investigated, indicating that [110] direction uniaxial stress is effective...
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