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This work presents SOI finFETs with fin width (Dfin) scaled to sub 15nm. The process flow provides robust Dfin scaling as depicted by the universal electrostatic scaling of the DIBL and sub-threshold swing (SS). The high field long channel mobility drops by ∼6% with Dfin scaling, however, DIBL and SS improves by ∼1.5X and ∼2X, respectively, for 20nm channel length n/pfinFETs. The effective current...
For several decades, the output from semiconductor manufacturers has been high volume products with process optimisation being continued throughout the lifetime of the product to ensure a satisfactory yield. However, product lifetimes are continually shrinking to keep pace with market demands. Furthermore there is an increase in dasiafoundrypsila business where product volumes are low; consequently...
Novel 3D stacked gate-all-around multichannel CMOS architectures were developed to propose low leakage solutions and new design opportunities for sub-32 nm nodes. Those architectures offer specific advantages compared to other planar or non planar CMOS devices. In particular, ultra-low IOFF (< 20 pA/mum) and high ION (> 2.2 mA/mum) were demonstrated. Moreover, those transistors do not suffer...
The increasing ubiquity of mobile embedded systems has been matched by the evolution of a variety of wireless network standards and technologies. The major constraints of wireless embedded systems are limitations of communication bandwidth, processing capabilities, and battery power. Remote wireless embedded systems often act as sensors, which provide data to a certain community. The exchange of data...
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