Serwis Infona wykorzystuje pliki cookies (ciasteczka). Są to wartości tekstowe, zapamiętywane przez przeglądarkę na urządzeniu użytkownika. Nasz serwis ma dostęp do tych wartości oraz wykorzystuje je do zapamiętania danych dotyczących użytkownika, takich jak np. ustawienia (typu widok ekranu, wybór języka interfejsu), zapamiętanie zalogowania. Korzystanie z serwisu Infona oznacza zgodę na zapis informacji i ich wykorzystanie dla celów korzytania z serwisu. Więcej informacji można znaleźć w Polityce prywatności oraz Regulaminie serwisu. Zamknięcie tego okienka potwierdza zapoznanie się z informacją o plikach cookies, akceptację polityki prywatności i regulaminu oraz sposobu wykorzystywania plików cookies w serwisie. Możesz zmienić ustawienia obsługi cookies w swojej przeglądarce.
Multipliers are the key components of systems viz. FIR filters, Microprocessors, Digital Signal Processors etc. which demands high performance. The performance of these applications mainly depends on the numbers of multiplication done in unit time. In real time multipliers the speed and power are the major criteria, thus faster and power efficient multipliers are needed. This paper focuses on the...
Power consumption in digital systems has become a major trade-off in portable battery based digital systems. Traditionally CMOS logic circuits are used to manufacture digital systems and the power delay product gives the average power consumed per unit switching activity in a CMOS logic. A power and delay reduction methodology based on DEMORGAN'S Laws is proposed and the proposed logical block is...
Increasing demand for the mobile, low energy systems has laid emphasis on the development of low power processors. Low power design has to be incorporated into fundamental computation units, such as multipliers. The optimization of the energy-delay product in such low power multipliers will enable energy efficient computation. This study proposes a power estimation tool to analyze different array...
Low power and high speed requirement is a challenging task in design of ALUs. Supply voltage scaling is promising approach because it reduces switching activities and active power but it degrades the performance and robustness. Recently a new like static circuit family called Feedback-Switch Logic (FSL) has been proposed. FSL is suitable for high speed and low power because it offers fast switching,...
Low power multipliers with high clock frequencies play an important role in today's digital signal processing. In this work, the performance analysis of Wallace-tree, Array and Baugh-Wooley multiplier architectures is carried out. Physical verification of all the sub-blocks is performed using HSpice to check their functionality and to optimize for low power by using transistor sizing. The layouts...
The paper presents a novel high speed and low power 15-4 Compressor for high speed and low power multiplication applications. The proposed compressor uses bit sliced adder architecture to exploit the parallelism in the computation of sum of 15 input bits by five full adders. The newly proposed compressor is also centered around the design of a novel 5-3 compressor that attempts to minimize the stage...
Podaj zakres dat dla filtrowania wyświetlonych wyników. Możesz podać datę początkową, końcową lub obie daty. Daty możesz wpisać ręcznie lub wybrać za pomocą kalendarza.