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This paper proposes a power-efficient capacitor-array-based digital-to-time converter (DTC) using a constant-slope approach. Fringe-capacitor-based digital-to-analog converter (C-DAC) array is used to regulate starting supply voltage of the constant slope fed to a fixed threshold comparator. The proposed DTC consumes only 15 μW from a 1V supply, while achieving fine resolution of 103 fs when running...
This manuscript includes chip measurements for a 32-bit Ripple-Carry Adder (“RCA”), demonstrating functionality for a supply voltage (“Vdd”) down to 84 mV. The low Vdd might be the lowest reported for comparable CMOS circuitry, not depending on special schmitt-trigger based logic or body biasing. Two 32-bit ripple-carry adders are implemented in 65 nm CMOS, having all gate lengths of 60 nm and 80...
Quantum-dot Cellular Automata (QCA) is an emerging nanotechnology to reduce size as well as power consumption of switching devices for Very Large Integrated Circuits (VLSI). Moreover QCA circuits offer an advantage of very high device density, high speed, high fan out, and lower circuit complexity. The QCA based circuits have been used for implementations of basic logic gates like AND, OR, NOT as...
The IC technology is tremendously growing day by day to improve the performance of the circuits structure in a compact and high density form. This tiny IC arena started and introduced the Quantum-dot cellular Automata (QCA) to overcome the pitfalls of conventional CMOS technology throughput. In order to bring a new phase of IC design in an optimized & efficient manner, we proposed, cascading serial...
Technology evolution brings new challenges to integrated circuits (IC) design. Parameter variation and complex design rules demand a great effort to create suitable design approaches to ensure manufacturability. Regular layout techniques allow a more accurate estimate of the circuit power and delay in early design steps. In this context, this work presents an evaluation of a set of basic cells candidates...
A high bandwidth critical path monitor (1 sample/ cycle at 4-5 GHz) capable of providing real-time timing margin information to a variable voltage/frequency scaling control loop is described. The critical path monitor tracks the critical path delay to within 1 FO2 inverter delay with a standard deviation less than 3 FO2 delays over process, voltage, temperature, and workload. The CPM is sensitive...
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