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An experimental 0.6-V 57.5-fJ/conversion-step 250-kS/s 8-bit rail-to-rail successive approximation (SA) analog-to-digital converter (ADC) implemented in a standard CMOS 0.18 μm digital process is presented. To overcome the input sampling switches limitation imposed by the low supply voltage we make use of a track-and-hold circuit based on a low-voltage, low-stress and reliable clock signal with a...
A new current mirror based all-pass, tunable phase shifter architecture is proposed in 0.18 um CMOS, after a brief introduction on phase shifter applications, and comparison between different implementation methods. In the new current-mode approach the cut-off frequency of transistor is the operational limit of the proposed phase-shifter architecture and power consumption for this design is 80 microwatts...
A low power Read-Out Integrated Circuit (ROIC) for a short-wave Infra-Red Focal Plane Array (IRFPA) is designed as a prototype for 1024??1024 image system. Ripple integration and readout scheme as well as highly efficient power management is introduced to this design in order to decrease total power dissipation. To overcome the charge sharing problem caused by this low power readout scheme, novel...
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