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This paper presents a 510nW 12-bit 200kS/s SAR-assisted SAR ADC in 40nm CMOS at 0.7V supply. A re-switching technique is proposed to suppress DNL spikes so that the size of DAC capacitor array can be minimized to reduce switching energy. A set of 2-way charge pump is used to decrease settling time constant and to increase sampling linearity. The prototype ADC achieves the DNL/INL performance of 0...
This paper presents a 0.9V-VDD sub-nW CMOS voltage reference based on dynamic operation with the absence of large resistors, hence occupying small chip area. The proposed voltage reference is based on the threshold voltage difference between high-Vt and normal-Vt transistors. Switched capacitors are used instead of resistors to reduce chip area and to enable dynamic operation. Moreover, the dynamic...
Detailed knowledge of a circuit’s timing is essential for performance optimization, timing closure, and generation of test patterns to detect small-delay defects. When an input transition is applied to the circuit’s inputs, the resulting delay is not only determined by the propagation path, but also influenced by the power-supply noise. We introduce a path-sensitization procedure which precisely controls...
Low-power multipliers are very important for reducing energy consumption of digital processing systems. This study provides the experience of applying an advanced version of our former Spurious Power Suppression Technique (SPST) on multipliers for high-speed and low-power purposes. To filter out the useless switching power, there are two approaches, i.e. using registers and using AND gates, to assert...
In this paper, a Linear Feedback Shift Register (LFSR), designed using MOS Current Mode Logic (MCML) is presented. Three different implementations of LFSR based on the three design methodologies of MCML D-Latch (D-Latch using traditional MCML style, D-Latch using switch-based MCML tri-state buffers and D-Latch using low power MCML tri state buffers) are realized. All simulations are performed in PSpice...
Full Adder performs addition and therefore in microprocessor and digital signal processor, it is used for arithmetic operation, for comparison and for access the address in memory. Improvement of this circuit would impart a greater impact on the performance of large systems where it has been employed. For improvement of power and delay performance in full adder, the 10T structure based static energy...
Power consumption is the greatest concern in current highly-integrated hardware-system design. The power reduction is targeted mostly through power management, implementing such techniques as clock gating, power gating, or voltage and frequency scaling. Due to growing complexity, the start-point in the design has moved from the register-transfer level to the system level. However, the power management...
This paper presents a low power D-latch designed using two low power tri-state MCML buffers. The proposed D-latch consumes less power as it makes use of low power tri-state buffers which promotes power saving due to reduction in the overall current flow in the circuit during the high impedance state. The proposed low power D-latch is simulated in PSPICE using 0.18μm TSMC CMOS technology parameters...
The paper presents design, analysis and fabrication of novel silicon-based, low power, non-volatile NEMS logic switches. Non-volatility is achieved by exploiting the Casimir effect and the van der Waals force at mechanical contact between an in-plane, laterally moveable transistor channel and two opposing side gates. Mechanical symmetry is implemented in the design for switching to be energy reversible...
In this paper we propose a low complexity full adder design featuring higher computing speed, lower operating voltage, and lower energy consumption. it uses the low power designs of the XOR and AND gates pass transistors and transmission gates, simulation results comparing the conventional cell to the standard implementation show its superiority different circuit structures and input patterns are...
High test power in logic BIST is a serious problem not only for production test, but also for board test, system debug or field test. Many low power BIST approaches that focus on scan-shift power or capture power have been proposed. However, it is known that a half of scan-shift power is compensated by test responses, which is difficult to control in those approaches. This paper proposes a novel approach...
High speed dynamic logic implementations have power consumption bottlenecks when driving large capacitive loads that occur in clock trees, memory bit/word lines and I/O pads. This severely limits their use in a System on Chip (SoC) at Gigabit rates. A novel dynamic logic gate that saves switching power by 50% with LC resonance is described. The stored energy on the load capacitance is transferred...
High speed dynamic logic implementations have power consumption bottlenecks when driving large capacitive loads that occur in clock trees, memory bit/word lines and I/O pads. This severely limits their use in a System on Chip (SoC) at Gigabit rates. A novel dynamic logic gate that saves switching power by 50% with LC resonance is described. The stored energy on the load capacitance is transferred...
Power management has emerged as a major design objective, both in functional and test mode, in most of the application domains that employ digital ICs. This paper presents a low power ATPG methodology for managing power both in shift and capture mode. The technique exploits the embedded clock gates and provides a good tradeoff between pattern count and reduction in switching activity without any significant...
This paper presents different performance metrics for single electron tunneling (SET) based static memory cell design using unique negative differential conductance (NDC), with emphasis on power optimization. The read/write operations for the memory cell are briefly discussed. All simulations are conducted using the Monte Carlo method from SIMON tools.
Sub threshold leakage current has increased dramatically with technology scaling and it consumes a significant portion of the total power. In order to reduce the leakage current, one of the efficient method is power gating. The main challenge in power gating is, to design switching fabric and power controller. In this paper the main aim is to implement power gating in semicustom design. For this we...
The energy consumed in switching the voltage on the power rail (VDD switching energy) is a significant overhead in systems using Dynamic Voltage Scaling (DVS) and/or power gating. In this work we propose and demonstrate the use of Stepped Supply Voltage Switching (SVS) for reducing VDD switching energy. We show the analysis, benefits, and overheads of using SVS for DSP algorithms implemented with...
For VLSI design in deep submicron technology, the bus energy reduction becomes more and more important. In this paper, we modify the bus-invert coding method to maximize the power consumption reduction of data bus. Unlike the conventional scheme in which the whole bus lines are considered for bus-invert coding, our scheme partitions the bus lines into several sub-buses and each partitioned sub-bus...
This paper presents a case for using Nano-Electro-Mechanical-System switches for power gating idle functional units of an embedded microprocessor. We achieve an average of 26% total energy savings, with a worst-case 5% increase in cycles. Our work includes detailed comparison with transistor switches, actuation circuitry design, identification of desired switch parameters, and device lifetime analysis
A low power SRAM macro is designed in 90nm TSMC model technology. The design is customized with Cadence Environment for minimal bit cell area, resulting in an area of 0.370 mm2. To reduce leakage power in standby mode, the SRAM architecture employs a dynamic supply voltage management scheme. The 64 kbits sub-array can run at 1.54 GHz at 1.0V supply voltage. Results demonstrated that the macro has...
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