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The iterative property of inverse butterfly permutation network makes it possible to implement shift operation with simple routing algorithm, which has high application value in cryptography, digital image processing and other fields. Based on the inverse butterfly network, this paper proposes a subword shift unit, which integrates the operations of subword rotation shift, subword logical shift and...
Hardening cryptographic algorithms against sidechannel attacks is a complex but crucial task in today's hardware implementations. One of the most promising countermeasures is Boolean Masking. Designers spend much effort to optimise and customise their masking schemes, but many proposed masked implementations were eventually broken, because they are somehow flawed - not necessarily restricted to a...
The electrical engineering approach to cache coherence is defined not only by the study of IPv7, but also by the natural need for A search 12. In fact, few cyberneticists would disagree with the valuation of write-back caches. Grafter, our new algorithm for cacheable configurations, is the solution to all of these problems.
Cryptography is one of the fundamental components for secure communication of data and authentication. However, cryptographic algorithms impose tremendous processing power demands that can be a bottleneck in high-speed networks. The implementation of a cryptographic algorithm must achieve high processing rate to fully utilize the available network bandwidth. To follow the variety and the rapid changes...
Advanced Encryption Standard (AES) is one of the most common symmetric encryption algorithms. The hardware complexity in AES is dominated by AES substitution box (S-box) which is considered as one of the most complicated and costly part of the system because it is the only non-linear structure. The proposed work employs a combinational logic design of S-Box implemented in Virtex II FPGA chip. The...
One of the most efficient methods for cracking passwords, which are hashed based on different cryptographic algorithms, is the one based on “Rainbow Tables”. Those lookup tables offer an almost optimal time-memory tradeoff in the process of recovering the plaintext password from a password hash, generated by a cryptographic hash function. In this paper, the first known such generic system is demonstrated...
Internet Protocol Security (generally shortened to IPSec) is a framework of open standards that provides data confidentiality, data integrity, and data authentication between participating peers at the IP layer. The Data Encryption Standard(DES) is used to encrypt and decrypt packet data at IP layer; it turns clear text into cipher text via an encryption algorithm. The decryption algorithm on the...
The need for small chip covered area in most handheld devices with out sacrifices in computational power introduces an interesting problem concerning expensive, computational intensive operations, like GF(2k) inversion which is widely used in cryptography. This paper addresses this problem by proposing a systolic inversion architecture for GF(2k) fields. This architecture is based on an extended analysis...
The most critical factors responsible for bottleneck in the design and implementation of high-speed AES (Advanced Encryption Standard) architectures for any resource constrained target platform such as an FPGA are Substitute byte/Inverse SubstituteByte and MixColumn/InverseMixcolumn operations. Most implementations conventionally make use of the memory intensive look up table approach for Substitute...
Over the past ten years, cryptographic algorithms have been found to be vulnerable against side-channel attacks such as power analysis attacks, timing attacks, electromagnetic radiation attacks and fault attacks. These attacks capture leaking information from an implementation of the algorithm in software or in hardware and apply cryptanalytical and statistical tools to recover the secret keys. A...
Modular multiplication is a very important arithmetic operation in cryptography systems and residue-based computation. This paper presents a synchronous modular multiplier that has variable computation latency depending on operand values. The modular reduction operation is based on SRT radix-2 division. However, the quotient selection function in certain stages is adapted for reducing delay and area...
Side-channel power analysis attacks have become a potent threat to the security of embedded cryptographic devices in microelectronic systems. In this paper, we present an overview of the various side-channel power analysis attacks and defenses (countermeasures) against side-channel power analysis attacks. We introduce these countermeasures and present analyses based on security strength, ease of integration...
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