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Recent literature on fast realizations of Connected Component Labeling has proposed single-pass algorithms and architectures that are particularly suited to hardware implementation. These architectures, however, impose input constraints unsuitable for real-time systems that have diverse interface specifications and bandwidth considerations. In this paper we present a streaming Connected Component...
This paper presents a hardware architecture for increased performance of color classification. In our architecture, color classification, based on an AdaBoost algorithm, identifies a pixel as having the color of interest or not. We designed the proposed architecture using Verilog HDL and implemented the design in a Xilinx Virtex-5 FPGA. The architecture for color classification can have 598 times...
In this study a discretized version of Cellular Neural Network (CNN) was implemented with an Hardware Description Language using forward Euler approximation. When the designs in literature were reviewed, it was seen that registers of the designs significantly affect occupied chip area. The introduced design is focused on reducing chip area by reducing register occupation while not causing design complexity...
In this paper efficient hardware architecture for deblocking filter in H.264 is presented. A parallel filtering order is proposed without violating the standard, and the architecture is implemented in pipelined dataptah. With the parallel filtering order the vertical edges and horizontal edges can be processed simutaneously, and the filtering efficiency is improved. The memory is arranged and orgnized...
Co-occurrence histograms of oriented gradients (CoHOG) is a powerful feature descriptor for pedestrian detection. However, its calculation cost is large because the feature vector for the CoHOG descriptor is very high-dimensional. In this paper, in order to achieve real-time detection on embedded systems, we propose a novel hardware architecture for the CoHOG feature extraction. Our architecture exploits...
The image foresting transform (IFT) is a general tool for the design of image processing operators based on dynamic programming. Silicon image forest transform (SIFT) is a fast 8-bit data architecture for IFT-based operators in FPGA. It can implement queue-based methods such as morphological reconstructions, watershed transforms, shape saliences, distance transforms, skeletonization, edge tracking,...
This article describes a new architecture for a parallel, digital image processor which performs several image processing tasks like segmentation, edge detection and noise removal. The architecture and algorithm modifications presented in this paper are aimed for reduction the FPGA area of a pixel, which represents basic image processing unit. The proposed modifications increase the functionality...
This paper presents a novel application specific instruction set processor specialized for block motion estimation. The proposed architecture includes an efficient register file system in terms of data reuse and parallel processing. Performances and area costs are presented for different levels of parallelism and register file dimensions. Various FPGA implementations of the architecture are further...
The implementation of a recently proposed IP core of an efficient motion estimation co-processor is considered. Some significant functional improvements to the base architecture are proposed, as well as the presentation of a detailed description of the interfacing between the co-processor and the main processing unit of the video encoding system. Then, a performance analysis of two distinct implementations...
A new processor architecture implementing the Discrete Time Cellular Neural Networks (DT-CNN) on FPGA is proposed. This architecture intends to process video images real time with 3times3 CNN templates and without the use of an external memory. The absence of the external memory decreases the cost and complexity of the system. The architecture is based on a single pipelined cell which is employed...
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