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In this paper, a Flash macro designed with high-density arrays of split-gate (SG) SuperFlash® cells, compatibly embedded in a 55 nm Low Power (LP) logic process is demonstrated with full functionality and excellent reliability at automotive temperature range. This split-gate Flash memory technology can be seamlessly and universally embedded in multiple logic process platforms, and can continually...
In this paper, an embedded 2T SONOS nonvolatile memory structure has been proposed for an embedded NVM cell in 90nm standard HVCMOS process. This nonvolatile cell can be fabricated by several steps such as ONO formation, cell junction implant, removal ONO films, those steps are non-critical processes and masks. The cell is operated by CHEI programming and BTBT-HHI erasing. The cell has been confirmed...
This paper reports 90nm embedded B4-Flash technology and its superior performance and reliability. Embedded B4-Flash has been implemented to certain 90nm CMOS process and fabricated its 16Mbit test array chip. B4-Flash superiority of high speed program and erase, high reliability has been confirmed by evaluating the 16Mbit test array chip and single bit test vehicle. Direct comparison of the retention...
The reliability of advanced embedded non-volatile memories has been discussed using the 2T-FNFN devices example. The write/erase endurance and the data retention are the most important reliability parameters. The intrinsic reliability mechanisms can be addressed through single cell evaluation, while the cell-to-cell variation determines the product level reliability. The cell-to-cell variation can...
Single, high energy, high LET, ions impacting on a Floating gate array at grazing or near-grazing angles lead to the creation of long traces of FGs with corrupted information. Every time a FG is crossed by a single ion, it experiences a charge loss which permanently degrades the stored information. If the ion crosses more than one FG, the threshold voltage of all those FGs interested by its track...
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