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In this paper, we investigate the optimization of device layout and embedded source/drain (eS/D) shape profile for strain engineered 22-nm node Si and SiGe p-channel trigate field-effect transistors by finite-element method simulations. A nested trigate layout with dummy gates is found to retain the maximum channel stress for all three conduction planes. The tradeoff between achievable mobility enhancement...
Gate density is ultimately increased to 2100 kGates/mm2 by pushing the critical design rules without increasing the circuit margin in 45 nm technology. Layout dependences for stress enhanced MOSFET including contact positioning, 2nd neighboring poly effect, and bent diffusion are accurately modeled for the first time. With the constructed design flow, gate length change of -2.8% to +3.6% and Idsat...
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