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Compressively-strained germanium-on-insulator (c-GeOI) substrates have been fabricated using the Smart Cuttrade technology. The technique is based on the optimized epitaxial growth process that reduces the threading dislocation density (TDD) in the strained Ge layer to the levels of 8middot105 /cm2. Pseudo-MOSFET characterization showed 67% hole mobility enhancement with respect to conventional GeOI...
The successful fabrication of hybrid SOI-GeOI wafers is reported. Process alternatives are documented by detailed characterizations. This co-integration achieves high hole mobility in Ge islands and high electron mobility in Si islands.
A non-classical device structure namely self-aligned quasi-silicon-on-insulator (SOI) metal-oxide semiconductor (MOS) field-effect transistor with pi-shaped semiconductor conductive layer (SA-piFET) is presented, seeking to improve the performance and upgrade the reliability of the SOI-based devices. Designed to equip with a SA single crystal silicon channel layer, plus a natural source/drain (S/D)...
This letter reports the first demonstration of an evanescent coupled germanium-on-silicon-on-insulator (Ge-on-SOI) metal-semiconductor-metal (MSM) photodetector with a novel silicon-carbon (Si:C) Schottky barrier enhancement layer. Through the insertion of a Si:C barrier layer between the metal/Ge interface, the hole Schottky barrier height phibh can effectively be enhanced to ~0.52 eV above the valence...
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