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We have developed analytically a threshold voltage model and explored the threshold voltage roll-off and drain-induced barrier lowering (DIBL) effects for undoped surrounding-gate (SG) MOSFETs. The model is derived by applying the Gauss law by considering an elemental area of the channel rather than using Poisson equation as implemented earlier. For this threshold voltage model, the threshold voltage...
Two dimensional numerical simulation of nanoscaled selective buried oxide (SELBOX) based MOSFET is performed. In this device an opening is provided under the device channel in the buried oxide (BOX). A comparative analysis of the SELBOX, bulk and SOI (Silicon-on-Insulator) devices for various performance measuring parameters has been done. The simulation study has revealed that by properly choosing...
A non-classical device structure namely self-aligned quasi-silicon-on-insulator (SOI) metal-oxide semiconductor (MOS) field-effect transistor with pi-shaped semiconductor conductive layer (SA-piFET) is presented, seeking to improve the performance and upgrade the reliability of the SOI-based devices. Designed to equip with a SA single crystal silicon channel layer, plus a natural source/drain (S/D)...
In this work, we have successfully demonstrated SONOS memories with embedded Si-NCs in silicon nitride by in-situ deposition method. The self-assembly silicon nanocrystals were in-situ deposited within the Si3N4 storage layer by dissociation of dichlorosilane (SiH2Cl2) gas to a high density of 9 times 1011 cm-2. This new structure exhibits larger memory windows for up to 6 V, better program/erase...
The power consumption and the matching will be the principal issues at the 32 nm node and below. In this context, Ultra-Thin Body devices are extensively studied for the end-of-roadmap CMOS. In this paper we present the SON technology, leading to the simple fabrication of sustained mono-Si nano-membranes over an empty tunnel, and discuss on the application of this process to build-up electronic devices...
Novel 3D stacked gate-all-around multichannel CMOS architectures were developed to propose low leakage solutions and new design opportunities for sub-32 nm nodes. Those architectures offer specific advantages compared to other planar or non planar CMOS devices. In particular, ultra-low IOFF (< 20 pA/mum) and high ION (> 2.2 mA/mum) were demonstrated. Moreover, those transistors do not suffer...
In this paper, by solving the 1-D Poisson equation using appropriate boundary conditions, we report a closed-form surface potential solution for all the three surfaces (gate oxide-silicon film interface, silicon-film-buried oxide interface, and buried oxide-substrate interface) of fully depleted silicon-on-insulator (SOI) MOSFETs by considering the effect of substrate charge explicitly. During the...
Systematic aging experiments have been performed on Silicon-On-Insulator p-MOSFET's synthesized by oxygen implantation (SIMOX). It is shown that the major degradation mechanism consists in electron injection in the buried oxide (BOX), even under normal operation conditions. The electron trapping into the BOX proceeds logarithmically in time. An analytical model is proposed to assess the trapping kinetics...
New short channel effects with nitride-oxide gate MOSFETs were found, where threshold voltage reduction occurs in a relatively long channel region. These effects would be explained by trapped charges or interface states induced by the mechanical stress at the Si and the nitride-oxide gate film in the course of the heat process.
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