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We report low Vt (Vt,Lg=1μm=±0.26V) high performance CMOS devices with ultra-scaled Tinv down to Tinv~8Å using a gate-first dual Si/SiGe channel low-complexity integration approach. Compared to a dual dielectric cap gate-first integration scheme, the devices fabricated with the novel scheme show for the same high-k/metal gate stack (1) 3Å reduction in nMOS and pMOS Tinv (2) 220mV lower long channel...
In order to improve the matching performance of the nMOSFET and pMOSFET threshold voltages in CMOS circuit, a novel p+ poly-SiGe gate CMOS device is described in this paper. With the change in work function and bandgap, the device effectively reduces the threshold voltage Vth of pMOSFET while the performance of nMOSFET is maintained. Moreover, the threshold voltage Vth of pMOSFET can be continuously...
Novel 3D stacked gate-all-around multichannel CMOS architectures were developed to propose low leakage solutions and new design opportunities for sub-32 nm nodes. Those architectures offer specific advantages compared to other planar or non planar CMOS devices. In particular, ultra-low IOFF (< 20 pA/mum) and high ION (> 2.2 mA/mum) were demonstrated. Moreover, those transistors do not suffer...
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