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Digital micro fluidics based biochips is expected to play an important role towards point-of-care diagnostics, drug discovery, prevention of bio-terrorism and other biochemical applications. Design and testing of biochips always remained a challenging area of research. Structural testing of these bio-MEMS is ensured by smooth movements of test droplets within the micro fluidic array. Partitioning...
Exhaustive speed testing of all the cores under extreme inter and intra-die process variations in a large chip multi processor (CMP) is expensive in terms of test time and may not guarantee full CMP functionality due to lack of coverage of timing failures induced by second-order effects such as cross talk, power/ground bounce and speed-limiting design bugs that are not "caught" by relevant...
This paper presents the “t-Ring” based DFX access architecture and the testability features of Intel's latest multi-core Itanium® processor. The architecture solves many common challenges of testing a multi-core CPU using distinctive and innovative solutions. At the core of the architecture is a hierarchical and scalable test access mechanism design providing flexible access for a variety of use models...
This paper addresses to questions of on-line testing for the computing circuits processing the approximate data. A problem of low reliability of on-line testing methods in checking the result is considered. This problem is connected to ignoring the natural time redundancy, which allows detecting the errors produced by the circuit fault during some interval of time. It reduces detection probability...
Multi-core architecture has become a mainstream in modern processor and computation-intensive chips. A widely-used multi-core architecture contains identical cores. This paper proposes a low-cost and scalable test architecture for a multi-core chip with identical cores. The test architecture provides test scalability by using a two-dimensional pipelined test access mechanism (TAM). Also, some scan...
On-line testing offers a promising method for detecting defects, fluidic abnormalities, and bioassay malfunctions in microfluidic biochips. To reduce product cost for disposable biochips, testing steps and functional fluidic operations must be implemented on pin-constrained designs. However, previous testing methods for pin-constrained designs do not optimize test schedules to reduce the number of...
Designing safety-critical systems is a complex process, and especially when the design is carried out at different levels of abstraction where the correctness of the design at one level is not automatically sustained over the next level. In this work we focus on time-triggered (TT) systems where the resources of communication and computation are shared among different applications to reduce the overall...
The 5 GHz IBM POWER6 processor (P6) and newest Z10 4.4 GHz processor utilized a custom combination of structural and functional testing delivering improved test costs and accelerated SPQL learning over previous IBM processor generations.
This paper describes several methodologies based on a pulsed laser beam to reveal the architecture of a high integrated SDRAM, and the different classes of Single Event Effects that can occur due to cosmic radiations. At cell level, laser is used to reveal an important technological parameter: the lithography process. At memory array level, laser is a powerful tool to retrieve cell physical arrangements,...
Software-based self-test (SBST) is increasingly used for testing processor cores embedded in SoCs, mainly because it allows at-speed, low-cost testing, while requiring limited (if any) hardware modifications to the original design. However, the method requires effective techniques for generating suitable test programs and for monitoring the results. In the case of processor core testing, a particularly...
In this paper, we investigate optimum radiation hardened by design (RHBD) for use against single-event transients (SET) using low-pass filters (LPF) including RHBD techniques against single-event upsets (SEU) for sequential logic in 45 -nm technology in a terrestrial environment. Three types of LPF were investigated regarding their SET pulse immunities, area penalties, and performance penalties. We...
The Niagara2 CMT system-on-chip incorporates many design-for-test features to achieve high test coverage for both arrays and logic. All the arrays are tested using memory built-in-self-test. This is supplemented with scan-based testing. Logic is tested with standard ATPG for slow-speed defects and extensive use of transition test, along with logic built-in-self-test for the SPARC cores, for at-speed...
A test strategy is described for a recent bit-level systolic array design. The test vectors are simple, being only of order n for an nxn array, and comparators on or off the chip compress the results into pass/fail signals.
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