The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
In this brief, we reported a ferroelectric versatile memory with strained-gate engineering. The versatile memory with high-strain-gate showed a >40% improvement on ferroelectric hysteresis window, compared to low-strain case. The high compressive stress induced from high nitrogen-content TaN enhances monoclinic-to-orthorhombic phase transition to reach stronger ferrolectric polarization and lower...
This paper presents a technical perspective for a high density DRAM especially a IM DRAM. From extrapolation of past trends in memory capacity vs. size, chip size will be 50 to 60 mm2. This will be realized by improving the cell structure, the dieletric layer for a cell or both. The good candidates are the corrugated capacitor cell (CCC) and stacked capacitor cell (STC). In transistor technology,...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.