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In this paper a 5Gb/s equalizer has been presented. It is designed to operate within USB 3.0 transceiver and compensates for frequency dependent losses introduced by transmission channel. For the reference signal, the clock and data recovery circuit has been used. This approach allowed to minimize the equalizer components. Critical equalizer building blocks have been implemented in GLOBALFOUNDRIES...
In this paper, we propose an ultra high-throughput LDPC decoder SOC to fulfill the requirement of IEEE 802.15.3c standard. By implementing a macro-layer fully parallel architecture, our proposed decoder takes only 4 clock cycles to finish one layered decoding iteration. Interconnection complexity problem introduced by high-parallel decoding is nicely solved by proposed reusable message permutation...
An all-digital fast frequency acquisition full-rate clock and data recovery (CDR) circuit for USB 2.0 applications without a reference clock is presented in this paper. The proposed digitally controlled oscillator (DCO) with an embedded time-to-digital converter (TDC) can recover the frequency of the synchronous data pattern in a very short time. In addition, the whole frequency acquisition can be...
The use of adaptive equalizers at the front end of receivers is becoming a necessity as the data rates increase without channel improvements. Adaptive equalizers can be implemented using data-aided or non-data-aided schemes, with the latter requiring less area and power. Previous non-data-aided adaptive schemes implement an asynchronous analog algorithm where the power spectrum of the received signal...
With a cut-off frequency in excess of 250GHz, nanometer-scale CMOS technology is rapidly expanding from Radio Frequency to mm-Waves applications. Frequency dividers are key building blocks for LO generation in wireless transceivers and clock synchronization in front-ends for wire-line and optical communications. Dividers based on traditional static CML latches work over a wide band but power dissipation...
The successive-approximation (SA) algorithm is traditionally used for low bandwidth applications because it requires n clock cycles or more to obtain n-bit resolution. However, the use of modern nanometer CMOS technologies and special design solutions overcome the speed limit, enabling conversion rates in the hundreds of MHz with very low power consumptions. This design uses the successive-approximation...
Trends in cable TV reception for data and video require simultaneous capture of many channels, e.g., 16, arbitrary located in the 48-to-1002MHz TV band. The challenges of integrating more than two zero-IF tuners on a single die could be simplified with a low-power 10b ADC that can digitize the entire TV band and be suitable for integration with baseband DSP. This work presents a 64χ inter leaved 2...
This paper demonstrates more than one order of magnitude improvement in 6b CMOS DAC design with a test circuit operating at 56Gs/s, achieving SFDR >;30dBc and EI\IOB>;4.3b up to the output frequency of 26.9GHz. Total power dissipation is less than 750mW and the core DAC die area is less than 0.6x0.4 mm2.
Next generation optical and electrical communications such as chip-to-chip serial links or 100GbE require very-high-speed transceivers. At tens of Gb/s, both transmitters and receivers suffer from inadequate bandwidth and high power consumption. One major difficulty arises from the performance degradation of FIR-based FFEs as the FF's CK-Q delay becomes significant to one bit period. Using passive...
In this paper, we present a low-power high-performance WiMAX chipset fully compliant with IEEE 802.16e specification corrigendum 1, 2 for mobile broad band access and WiMAX Forum System Profile Wave2. The chipset is comprised of a 632.7mW modem/router chip and a 364mW RF transceiver chip, both devel oped in 65nm CMOS. A fully programmable SIMD processor is used for WiMAX baseband and only parts of...
Burst-mode clock and data recovery circuits (BMCDR) are widely used in passive optical networks (PON) [1] and as a replacement for conventional CDRs in clock-forwarding links to reduce power [2]. In PON, a single CDR performs the task of clock and data recovery for several burst sequences, each originating from a different source. As a result, the BMCDR is required to lock to an incom ing data stream...
The authors presents a 100GbE gearbox LSI combining a 10:4 MUX and a 4:10 DEMUX. This gearbox LSI implemented in 65nm CMOS decreases power dissipation by 75% compared to that of a conventional LSI.
As the latest product of Godson processor series, the Godson-3B processor is an 8-core high-performance general-purpose processor implemented in 65nm CMOS low-power general-purpose mixed process with 7 layers of Cu metallization. Godson-3B contains 582.6M transistors (including 4MB L2-cache) within 299.8mm2 area. The number of signal pins in Godson-3B is 654. The highest frequency of Godson-3B is...
ADC-based receivers allow for extensive equalization in the digital domain and therefore can easily compensate for channel loss at higher data rates. Digital equalization can be implemented as an FFE or DFE. An adaptive FFE is straight forward to implement, as it relies on magnitudes only (not phases) of the blind samples, however, it enhances the quantization noise of the ADC. A DFE has better noise...
The jitter of the sampling clock of an analog-to-digital converter (ADC) is measured by a stochastic time-to-digital converter (TDC). The measured jitter data are used to correct the ADC sampling error and improve its signal-to-noise ratio (SNR). The same ADC is used to calibrate the TDC in the background. Both the TDC and the ADC operate at a sampling rate of 80 MS/s. Fabricated in a 65 nm CMOS technology,...
This paper presents a twice the supply voltage bootstrapped switch with the proposed rise time accelerator that has high linearity and fast rising with single phase clock input at low voltage. The proposed rise time accelerator improves rising time and ensures circuit operation at extremely low supply voltage without any complex timing generation circuit. The prototype switch is designed in 65nm CMOS...
This paper introduces new charge and discharge paths to speed up the turn-on and turn-off process of bootstrapped switch. In the mean time, linearity is improved without increasing capacitance or area. The proposed switch is designed in SMIC 65nm CMOS process and the results indicate that total harmonic distortion (THD) of 95dB is acquired when 103MHz input signal is sampled at 1Gsps.
A high-speed multi-phase oscillator based on self-timed ring is proposed. Self-Timed Rings (STR) are promising approach for designing high-speed serial links and clock generators. The architecture of STR allows us to achieve a maximum frequency with a multiphase outputs since the oscillation frequency is not only depending on the number of stages but on the number of “tokens” and “bubbles” circulating...
This paper presents a design for an on-chip high-speed clocked-comparator for high frequency signal digitization. The comparator consists of two stages, amplification and regenerative, comprising a total of 10 MOS transistors. The design is implemented in 65nm CMOS technology. Also, the paper presents a new cost effective technique for measuring the maximum speed of the clocked comparator. The measurement...
This paper presents a 0.6-V voltage doubler and a 0.6-V clocked comparator in 65 nm CMOS. For the multi-phase sampling application, such as charge-domain correlator for impulse UWB receivers or analog-to-digital converter, the proposed voltage doubler can reduce the power consumption and the chip area by half compared to the conventional one. The non-overlapping complementary clock generator used...
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