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Many important fields for the application of semiconductor ICs (e.g. digital communication networks, factory automation, office automation) are governed by processing digital data streams. Often these data streams are split into parts, which are processed separately. Afterwards usually synchronization is necessary, because different latencies occur in each processing unit. A delay circuit, which is...
This paper presents an implementation of a binary pulse-position modulator (2-PPM) for impulse-radio ultra-wideband (IR-UWB) systems, capable of producing an appropriate signal to drive the final output stage of an ultra narrow pulse generator. Compared to the usual circuits based on voltage-controlled delay lines, this novel scheme uses digital signal processing of the clock and data signals with...
This paper presents a temperature and supply voltage variation-tolerant CMOS relaxation oscillator which is suitable for ultra-low power systems. A low-power low-cost half-period pre-charge compensation scheme is proposed to eliminate influences of the delay of the comparator and the RS latch on the frequency stability of the relaxation oscillator. In a clock period consisting of four working stages...
A high-speed low-power 1:16 demultiplexer with a novel symmetrical-edge-delay sense amplifier is presented in this paper. The traditional Sense-Amplifier-Based Flip-Flop (SAFF) has asymmetric rising and falling edges with the fact that the falling edge lags the rising edge the time of a gate delay, which has become a bottleneck of speed. In order to overcome the problem of nonsymmetry of output data...
A scalable 7.0-Gb/s/lane, 6-lane serial link transceiver for chip-to-chip NRZ data communication is described. Its serializing transmitter uses a new circuit topology, with data-controlled pulse generation followed by pulse-controlled serialization, and provides improved bandwidth and power efficiency with the elimination of on-chip NRZ signaling and retiming while preserving the bandwidth benefit...
The performance of priority encoder circuits is usually limited by the delay associated with the propagation of the priority token, however, proper design in the architectural level can reduce the delay stages to the order of O(log n). Furthermore, power dissipation and area pose an increasingly important concern in modern circuit design, thus the development of suitable techniques is essential. This...
In high-speed serial communication interface circuits, a high-performance slicer is essential. This paper presents an improved slicer based on SA/FF (Sense Amplifier/Flip Flop) and extracts the sample function of whole circuit system. The results show that the proposed configuration can achieve a regeneration gain of 61.8dB and a −3dB bandwidth of 10GHz. The power consumption of the new structure...
A low-spur PLL is desirable for many applications since it avoides mixing unwanted blocker signals, prevents emission mask violations or minimizes jitter in the clock source. Internal spurs result from the nature of PLL operation and include reference spurs and fractional spurs when the PLL is operated in fractional-N mode. External spurs are caused by nearby disturbances, such as coupling from other...
Injection-locked clock multipliers (ILCMs) achieve superior phase noise compared to conventional PLLs [1, 2]. In its simplest form, an ILCM is an oscillator into which a train of narrow pulses is injected at reference frequency FREF as shown in Fig. 10.6.1. If the free-running frequency, FFR, of the oscillator is tuned close to NFREF (N=4, in Fig. 10.6.1), injected pulses phase lock the oscillator...
Continuous-time delta-sigma modulators (CT-DSMs) are well suited for the baseband ADC of an LTE-A receiver. To boost user throughput and increase network capacity, CT-DSMs will need to increase signal bandwidth (BW) while maintaining sufficient dynamic range (DR) and good power efficiency. For example, 5 downlink component carriers are no longer sufficient to meet the ITU requirement for IMT-advanced...
Signaling over chip-scale global interconnect is consuming a larger fraction of total power in large processor chips, as processes continue to shrink. Solving this growing crisis requires simple, low-energy and area-efficient signaling for high-bandwidth data buses. This paper describes a balanced charge-recycling bus (BCRB) that achieves quadratic power savings, relative to signaling with full-swing...
The amount of data traffic is increasing year by year as the number of data-rich services like cloud services and streaming services are increasing. The number of switch modules between servers should decrease to lower latency, and several servers in each rack should be connected to one switch module with cables in a data centre. Using copper cables to connect racks is attractive in terms of cost...
A dual-rate hybrid DAC is proposed in [1] that shows a path toward high speed/linearity in scaled technology. In this hybrid architecture, the resolution of the DAC is achieved through an oversampled LSB path, while its output power is mostly delivered by a Nyquist MSB path, resulting in a reduced number of current-steering cells and relaxed amplitude-matching requirement via digital pre-distortion...
A processor executes a computing job in a certain number of clock cycles. The clock frequency determines the time that the job will take. Another parameter, cycle efficiency or cycles per joule, determines how much energy the job will consume. The execution time measures performance and, in combination with energy dissipation, influences power, thermal behavior, power supply noise and battery life...
As compared to static logic, domino logic circuits are always preferable for high performance circuit designs because of their less number of transistor requirement and high operational speed. Due to the presence of charge sharing problem and less noise tolerance this logic is not broadly accepted for all logic designs. The desired output of the circuit can change with a little noise pulse in the...
This paper presents a novel CAN transceiver based on a highly-digitized architecture designed and fabricated in 0.14µm high-voltage SOI CMOS. This advanced BCD process allows the implementation of this innovative architecture which combines digital and high-voltage analog circuits. Hence, the output stage can be split in multiple unit cells successively enabled or disabled by a shift register. It...
As sensor digitization for IoT-applications, this paper presents an all-digital MEMS gyro-sensor circuit method, using TAD (Time-A/D converter)-based digital synchronous detection (TAD-DSD) by applying entirely all-digital time-domain processing, which uses no conventional methods such as analogmixers, -filters and -ADCs. The proposed method involves twostep processing: 1) voltage-signal levels of...
We propose a high-resolution on-chip propagation delay measurement scheme. The scheme uses a pair of coherent equivalent-time sampling 1-bit digitizers. The scheme does not require complex circuits to be added on-chip, has reasonable test-time, and is not liable to the "bunching" effect. A test-chip was fabricated to characterize the propagation delay of a 65nm CMOS programmable I/O buffer...
This paper presents a fully digital delay locked loop (DLL) that can acquire lock in four clock cycles with a resolution of a 1/4 NAND-delay. The proposed DLL with a multi-dither-free phase detector acquires the initial lock in four clock cycles with 1/2 NAND-delay. Then, it utilizes a multi-dither-free phase detector, a region accumulator, and phase blenders, to improve the resolution to a 1/4 NAND-delay...
This paper presents a novel ultra-low-power dual-phase current-mode relaxation oscillator, which produces a 122 kHz digital clock and has total power consumption of 14.4 nW at 0.6 V. Its frequency dependence is 327 ppm/°C over a temperature range of −20° C to 100° C, and its supply voltage coefficient is ±3.0%/V from 0.6 V to 1.8 V. The proposed oscillator is fabricated in 0.18 μm CMOS technology...
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