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In this paper, we aim at increasing the strength of weak arbiter physical unclonable function (APUF) which are vulnerable to modeling attacks because of low uniqueness and randomness. We propose a unique technique which takes n × 1 challenge-response pairs (CRPs) from APUF and combines them with ring oscillators (ROs) implemented on the same FPGA to get n × n CRPs. We claim the proposed technique...
Recent deployments of FPGAs as compute resources in data centers have raised security concerns. One concern is how to prevent user-deployed logic in the FPGA from accessing privileged data such as physical addresses or raw network traffic. Addressing this issue uses the concept of ‘privileged’ mode FPGA logic that is kept separate from ‘user’ mode logic. Logical separation can be achieved with design...
In this paper, we propose and implement two electronic control unit (ECU) architectures for real-time automotive cyber-physical systems that incorporate security and dependability primitives with low resources and energy overhead. These ECUs architectures follow the multiprocessor system-on-chip (MPSoC) design paradigm wherein the ECUs have multiple heterogeneous processing engines with specific functionalities...
The Intrusion Detection Systems (IDS) is becoming important and quite timing/space consuming due to the increasing volume of explosive data flood. During the past decades, there have been plenty of studies proposing software mechanisms to exploit the temporal locality in the IDS systems. However, it requires considerable memory blocks to store the redundancy table, therefore, the performance as well...
The number of connected Internet of Things (IoT) devices was about 8.9 billion in 2012 and it is statistically estimated to grow up to 50 billion devices in the beginning of 2020. The security of the IoT plays an important role in the correct and advantageous functionality of the interconnected devices. For efficiency considerations, some of the IoT data processing is optimal to be implemented in...
IPsec is a suite of protocols that adds security to communications at the IP level. However, the high computing power required by the IPsec algorithms limits network connection performance. The paper presents the hardware implementation of IPsec gateway in FPGA. Efficiency of the proposed solution allows to use it in networks with data rates of several Gbit/s.
To protect the implementation of the standard Secure Hash Algorithm (SHA) against attacks. We have proposed a number of countermeasures. This paper present a proposed new fault detection scheme. It is based on the hybrid redundancy. The simulation results prove that the fault coverage achieves 99.999% for our scheme proposed. Also, our proposed detection scheme has been implemented on Xilinx Virtex-II...
While the use of reconfigurable computing for tasks such as packet header processing or deep packet-inspection in high-speed networks has been widely studied, efforts to extend the technology to application-level processing have only recently been made. One issue that has prevented wider use of reconfigurable platforms in that context is the unfamiliar programming environment: Such systems commonly...
In this paper we present a prototype of a measurement system for an electric car charging station, which provides much more than only battery charging. In addition to the core tasks, namely to measure the amount of transferred energy, and to organise the billing with the provider, a charging station must satisfy numerous other requirements. These include e.g. several safety aspects like the communication...
The cryptographic hash algorithm has been developed by designers with the goal to enhance its performances in terms of frequency, throughput, power consumption and area. The cryptographic hash algorithm is implemented in many embedded systems to ensure security. It is become the default choice to ensure the information integrity in numerous applications. In this paper, we propose a pipelined architecture...
Security has become a very demanding parameter in today's world of speed communication. It plays an important role in the network and communication fields where cryptographic processes are involved. These processes involve hash function generation which is a one-way encryption code used for security of data. The main examples include digital signatures, MAC (message authentication codes) and in smart...
Hardware Trojan horses are a realistic threat for both ASIC and FPGA systems. Ring Oscillators (ROs) can be used to detect the presence of malicious hardware functionality. The length of an RO is a significant parameter for detecting efficiently malicious logic (sensitivity) while maintaining a low space and power profile. We explore through simulation the effect of the RO length on detecting different...
FPGAs are widely deployed nowadays. Besides offering powerful computation capacity, contemporary FPGAs also provide many security features such as bitstream protection. The security of these features is dependent on the security of the keys embedded in the FPGA, which is usually generated by the vendor. This type of architecture has a shortcoming that the FPGA vendor knows everything and becomes the...
TCM (Trusted Cryptography Module) is the core of national trusted computing technology. This paper proposes the extending method of TCM in the embedded system, which is implemented on ARM embedded platform. After hardware architecture of trusted computing PC platform that is defined by TCG is researched and universal external interface of embedded platform is analyzed, SPI bus is selected to extend...
FPGA has been used in many fields such as space, military, auto. It is the best choice of cipher protocol and artithmetic achievement. Its security has been a focus. In this paper, the authors design a Hardware Trojan of transmitting key information towards FPGA. It is important to realize the implement mechanism and raise the attention to IC security.
Elliptic Curve Digital Signature Algorithm (ECDSA) provides several security services for resource-constrained embedded devices. It can be the target of attacks as Side-channel attacks. The ECDSA level security can be enhanced by tuning several parameters as key size and the security level of each ECDSA elementary modules such as point multiplication, hash function and pseudo random number generators...
This work is related to System-On-A-Chip architectures and design methodologies, for cryptographic algorithms implementations. Alternative approaches are presented, for architecture and architectures for block ciphers, stream ciphers, and hash functions. The presented algorithms are the most wide used, in all certain of modern applications. Implementation aspects are given for both ASIC and FPGA integration...
Field-programmable gate arrays (FPGAs) are widely used in telecommunication due their substantial computational power and flexibly designed architecture. These features become especially important for applications of low transmission latency such as those supported by Distributed Multimedia Plays (DMP) architecture. Thus FPGAs are chosen in this work as the core building block of the system. Complex...
Steganography is one of the most powerful techniques to conceal the existence of hidden secret data inside a cover object. Images are the most popular cover objects for steganography, and thus the importance of image steganography. Embedding secret information inside images requires intensive computations, and therefore, designing steganography in hardware speeds up steganography. This work presents...
This paper describes a new approach for establishing security in communication satellites for prevention of hackers transpire. Nowadays, by increasing of the needs for world mobile communications, using of the satellites is necessary. Therefore security for transmitted information between the satellites and ground stations is really important. This paper presents a hardware firewall and it's implementation...
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