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Spin-Transfer Torque Random Access Memory (STTRAM) is one of the emerging Non-Volatile Memory (NVM) technologies especially preferred for the Last Level Cache (LLC). The amount of current needed to switch the magnetization is high (∼100ßA per bit). For a full cache line (512-bit) write, this extremely high current results in a voltage droop in the conventional cache architecture. Due to this droop,...
Energy efficient computing has become the key to enable the portability of new applications onto mobile devices which need to be always smaller and more powerful. As the technology node shrinks, the leakage current increases exponentially in deep submicron CMOS, so that new strategies are required in integrated systems to save power without limiting processing performances. One of the solutions is...
In this paper we demonstrate an energy-reduction strategy that relies on the stochastic long-tail nature of the STT-RAM write operation. To move away from the traditional worst-case approach, the per-cell write process is continuously monitored and is terminated as soon as each cell's state matches the written state. Since the average write duration is far shorter than the worst-case duration, the...
Detailed description Non-volatile Memory Based on Magnetic Tunnel Junction is presented. A dynamic Verilog-A behavioral model and a Spice macro-model of a single memory cell was developed. The advantages of the proposed models demonstrated on a next generation revolutionary Magnetic Random Access Memory (MRAM) which we offer to implement on an integrated circuit (IC) based on CMOS technology. The...
In this paper, we propose a run-time strategy for managing writes onto last level cache in chip multiprocessors where STT-RAM memory is used as baseline technology. To this end, we assume that each cache set is decomposed into limited SRAM lines and large number of STT-RAM lines. SRAM lines are target of frequently-written data and rarely-written or read-only ones are pushed into STT-RAM. As a novel...
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