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This paper presents a sigma-delta modulator of two-order with switched-capacitors (SC) techniques for low power in 0.18 um CMOS process. Without continues current transmission SC techniques present a discrete low power system. And a low power op amplifier with discrete common-mode feedback and a dynamic comparator is also designed. This new amp works under the supply of 1.8 v and with the direct current...
This paper demonstrates the low energy operation of 4-bit ripple carry adder (RCA) employing two phase clocked adiabatic static CMOS logic (2PASCL) circuit techniques. We evaluate NOT, NAND, XOR and NOR logic gates on the basis of the 2PASCL topology using SPICE implemented using 0.18 ??m CTX CMOS technology. For NOT circuit, analytical and simulation values are compared. By removing the diode from...
This paper describes the principle with the quadrature reference clocks in dual-loop clock and data recovery circuit. The traditional scheme of generating quadrature clock is analyzed, and a new algorithm with phase interpolation and selection is presented after the modification of the circuit in existence. This algorithm enhances the jitter tolerance of input datum. The scheme is realized with CMOS...
While the CMOS analog circuits can be designed with the minimum-gate-length of the fabrication process in the alpha-power law MOSFET model, the length of a MOSFET gate has been chosen to be a larger scale than the minimum-gate-length in the conventional Shockleypsilas square model. In this paper, we describe a 6-b 100 MSPS CMOS current steering digital-to-analog converter (DAC) with the alpha-power...
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