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This paper proposes a novel circuit transformation based method to generate tests for cross-wire open, transistor stuck-open and delay faults inside CMOS cells/gates as well as transition faults in interconnects between gates using a unified model, called dynamic aggressor-victim type of bridging fault model (DBF). The unified fault model allows handling all these faults in one ATPG run and thus the...
This article takes a first step in the field of secured circuits testing and characterization of associated fault models. We analyze the electrical impact of the resistive bridge defect in deep-submicron secured circuits, implemented in WDDL and in SecLib. The quality of this analysis is verified by SPICE simulations. It is shown that the detection of defect depends on the bridging resistance value...
This paper presents gate level delay dependent probabilistic fault models for CMOS circuits operating at sub-threshold and near-threshold supply voltages. A bottom-up approach has been employed: SPICE simulations have been used to derive higher level error models implemented using Verilog HDL. HSPICE Monte-Carlo simulations show that the delay dependent probabilistic nature of these faults is due...
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