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CMOS utilizing high mobility III-V/Ge channels on Si substrates is expected to be one of key devices for high performance and low power advanced LSIs in the future. In addition, the heterogeneous integration of these materials with Si can provide a variety of More-than-Moore and Beyond CMOS applications, where various III-V/Ge functional devices can be co-integrated. In this presentation, we review...
In this paper, Single Material Double Workfuntion Gate (SMDWG) MOSFET was proposed, which is compatible with CMOS technology and has the performance as Dual Material Gate (DMG) MOSFET. The capacitance performance of SMDWG MOSFET is simulated by MEDICI. Comparison with p+ gate and n+ gate MOSFET are made, and the differences are discussed in detail. The SMDWG MOSFET device operating at subthreshold...
A non-classical device structure namely self-aligned quasi-silicon-on-insulator (SOI) metal-oxide semiconductor (MOS) field-effect transistor with pi-shaped semiconductor conductive layer (SA-piFET) is presented, seeking to improve the performance and upgrade the reliability of the SOI-based devices. Designed to equip with a SA single crystal silicon channel layer, plus a natural source/drain (S/D)...
This paper discusses the design of a 60 GHz low noise amplifier (LNA) using a standard low power SOI CMOS process from ST Microelectronics. First, we outline the technology as well as the mm-wave design challenges. Using recent work on coplanar waveguide (CPW) modeling, we describe how it's possible to use parametric, 3D electromagnetic simulation to complete or replace analytical models of on-chip...
For several decades, the output from semiconductor manufacturers has been high volume products with process optimisation being continued throughout the lifetime of the product to ensure a satisfactory yield. However, product lifetimes are continually shrinking to keep pace with market demands. Furthermore there is an increase in dasiafoundrypsila business where product volumes are low; consequently...
This work aims to examine and analyze carefully the effects of block oxide length (LBO) in a 40 nm multi-substrate-contact field-effect transistor (MSCFET). In addition, the proposed structure is based on the self-aligned (SA) gate-to-body technique. In the MSCFET design the two key parameters are the length and the height of the block oxide which are so sensitive to the short-channel effects (SCEs)...
The power consumption and the matching will be the principal issues at the 32 nm node and below. In this context, Ultra-Thin Body devices are extensively studied for the end-of-roadmap CMOS. In this paper we present the SON technology, leading to the simple fabrication of sustained mono-Si nano-membranes over an empty tunnel, and discuss on the application of this process to build-up electronic devices...
Continuous scaling, necessary for enhanced performance and cost reduction, has pushed existing CMOS materials much closer to their intrinsic reliability limits, forcing reliability engineers to get a better understanding of circuit failure. This requires that designers will have to be very careful with phenomena such as high current densities or voltage overshoots. In addition to the reliability issues,...
Graphene is a possible candidate for advanced channel materials in future field effect transistors. This presentation gives a brief overview about recent experimental results in the field of graphene transistors for future electronic applications.
Transconductance (gm) enhancement in n-type and p-type nanowire field-effect-transistors (nwFETs) is demonstrated by introducing controlled tensile strain into channel regions by pattern dependant oxidation (PADOX). Values of gm are enhanced relative to control devices by a factor of 1.5 in p-nwFETs and 3.0 in n-nwFETs. Strain distributions calculated by a three-dimensional molecular dynamics simulation...
Novel 3D stacked gate-all-around multichannel CMOS architectures were developed to propose low leakage solutions and new design opportunities for sub-32 nm nodes. Those architectures offer specific advantages compared to other planar or non planar CMOS devices. In particular, ultra-low IOFF (< 20 pA/mum) and high ION (> 2.2 mA/mum) were demonstrated. Moreover, those transistors do not suffer...
This paper focuses on the TCAD assessment of Gate Electrode Workfunction Engineered Recessed Channel (GEWE-RC) MOSFET as a solution to CMOS technology for high performance analog applications in terms of speed-to-power dissipation, device efficiency and hot electron injected gate current design parameters. Moreover, the paper also discusses the effect of gate stack architecture and various design...
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