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This work, for the first time, examines the work function fluctuation (WKF) and interface trap fluctuation (ITF) using experimentally calibrated 3D device simulation on high-κ/metal gate technology. The random WKs result in 36.7 mV threshold voltage fluctuation (σVth) for 16 nm N-MOSFETs with TiN gate, which is rather different from the result of averaged WKF (AWKF) method [1] due to localized random...
Scaling limit of ultra-thin-body SOI-MOSFETs is quantitatively evaluated using device simulation, which takes into account full-band structure, quantum mechanical effects and quasi-ballistic effects. It was found that the SOI thickness (tSOI) cannot be decreased less than 3nm due to severe surface roughness (tSOI fluctuation) scattering. Further considering substrate bias optimization for both On-...
The problem of V,ι, local variations for the state-of-art MOSFETs imposes a limit on the scaling of the technologies, and therefore, it is an urgent issue to understand causes and find solutions. The variety of the Vth local variation sources can be cited. However, the main causes of the Vth variability have not been confirmed yet. The investigations of the mechanism are crucial to improve the Vth...
A non-classical device structure namely self-aligned quasi-silicon-on-insulator (SOI) metal-oxide semiconductor (MOS) field-effect transistor with pi-shaped semiconductor conductive layer (SA-piFET) is presented, seeking to improve the performance and upgrade the reliability of the SOI-based devices. Designed to equip with a SA single crystal silicon channel layer, plus a natural source/drain (S/D)...
The minimum operating voltage (Vmin) of nano-scale LSIs is investigated, focusing on logic gates, SRAM cells, and DRAM sense amplifiers in LSIs. The Vmin that is governed by SRAM cells rapidly increases as devices are miniaturized due to the ever-larger variation of the threshold voltage (VT) of MOSFETs. The Vmin, however, is reduced to the sub-one-volt region by using repair techniques and new MOSFETs...
Random telegraph noise (RTN) in scaled FETs is one of the biggest concerns in the present and future LSIs. However, RTN in high-kappa gate dielectric FETs have not been fully studied yet. In this paper, we have studied RTN in high-kappa pFETs in comparison with that in SiO2 pFETs. It is found for the first time that the reduction of the RTN amplitude (DeltaId/Id) by the surface holes is smaller in...
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