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Self-healing systems can restore their original functionality by use of run-time self-reconfiguration, a feature supplied by state of the art FPGA devices. Commonly, integrity checks are performed by reading back the device configuration and validating its hash value. Systems which are prone to tampering and piracy of intellectual property may disable configuration readback, which renders this method...
Cryptography is one of the fundamental components for secure communication of data and authentication. However, cryptographic algorithms impose tremendous processing power demands that can be a bottleneck in high-speed networks. The implementation of a cryptographic algorithm must achieve high processing rate to fully utilize the available network bandwidth. To follow the variety and the rapid changes...
Chaotic encryption schemes are believed to provide a greater level of security than conventional ciphers. In this paper, a chaotic stream cipher is first constructed and then its hardware implementation details using FPGA technology are provided. Logistic map is the simplest chaotic system and has a high potential to be used to design a stream cipher for real-time embedded systems. The cipher uses...
Integrating reconfigurable computing with high-performance computing, exploiting reconfigurable hardware with their advantages to make up for the inadequacy of the existing high-performance computers had gradually become the high-performance computing solutions and trends. Based on comprehensively investigating the reconfigurable technologies, the paper presented a high-performance computing scheme...
Recently, DES has been the most widely used symmetric block cipher for information security. But many powerful attacks, such as differential attack and linear attack had been proposed for cryptanalyzing DES. This paper gives an introduction and theoretical analysis of DES Algorithm and proposes a new design of encryption key and S-box to improve the algorithm performance. The hardware language VHDL...
In this paper, we propose a high-speed parallel GF(2128) bit multiplier for Ghash function in conjunction with its FPGA implementation. Through the use of Verilog the designs are evaluated by using Xilinx Vertax5 with 65 nm technic and 30,000 logic cells. The highest throughput of 30.764 Gpbs can be achieved on Virtex5 with the consumption of 8864 slices LUT. The proposed design of the multiplier...
In the context of FPGAs, system downgrade consists in preventing the update of the hardware configuration or in replaying an old bitstream. The objective can be to preclude a system designer from fixing security vulnerabilities in a design. Such an attack can be performed over a network when the FPGA-based system is remotely updated or on the bus between the configuration memory and the FPGA chip...
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