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We have successfully fabricated InGaAs-OI tri-gate nMOSFETs, for the first time. The devices were depletion-type (p-n junction-less) nFETs with Fin-channel width (Wfin) down to 20 nm and had metal source/drain structures. It was experimentally demonstrated that Wfin scaling effectively improved cut-off properties at Nd up to 5 × 1018 cm−3 and the electron mobility in the narrowest channel (Wfin =...
We present the first demonstration of a III-V MOSFET heterointegrated on a large diameter Si substrate and fabricated with a VLSI compatible process flow using a high-k/metal gate, self-aligned implants and refractory Au free ohmic metal. Additionally, TXRF data shows that with the correct protocols III-V and Si devices can be processed side by side in the same Si fabrication line The Lg = 500 nm...
For the simulations of C -V characteristics and mobilities a homogenous channel HOI PMOS structure is simulated. The thicknesses of the top and bottom oxide are 1 nm and 10 nm, respectively. The thicknesses of the channel stack layers are tsSi(cap) = 2 nm, tsSiGe = 20 nm, and tsSi = 4 nm. The thickness of the bulk layer below the bottom oxide is 800 nm. The Ge contents in the strained Si1-zGez layer...
Impact of area scaling (especially narrow channel) on Vt lowering by La incorporation in high-k gate NMOSFETs is reported for the first time. It is clarified that Vt becomes higher in narrower channel for La-containing high-k gate. Efforts are made to ascribe the strong dependence of Vt on gate width to less effectiveness of La compared to wider channel. Influence of channel orientation at STI edge...
This paper presents an innovative structure based on 3 dimensional integration technology, where ultra thin inter layer dielectric enables a dynamic threshold voltage (VTH) control. A sequential process flow is proposed to fabricate 3D devices with dynamically tunable VTH. This ability can be exploited to design SRAMs cells with increased stability and surface density compared to planar technology...
Continuous scaling, necessary for enhanced performance and cost reduction, has pushed existing CMOS materials much closer to their intrinsic reliability limits, forcing reliability engineers to get a better understanding of circuit failure. This requires that designers will have to be very careful with phenomena such as high current densities or voltage overshoots. In addition to the reliability issues,...
Plasma-exposed Si surface related to Si recess in source/drain region was investigated in detail for various superposed bias configurations with frequencies of 13.56 MHz and 400 kHz. Two different bias powers were utilized by an inductively coupled plasma reactor (ICP). The surface layer (SL) and the interfacial layer between the SL and Si substrate (IL) were analyzed by spectroscopic ellipsometry...
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