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P-type Schottky barrier nanowire metal-oxide-semiconductor field-effect transistors are simulated with a rigorous quantum mechanical approach. The multi-band k·p method is employed for the description of hole transport in the silicon region while the parabolic effective mass Hamiltonian is used for the metallic source and drain. A characteristic transition from entirely thermionic transport to entirely...
We present the reliabilities in compressively strained SiGe channel pMOSFETs. A Si capping layer in SiGe channel pMOSFETs improved the negative bias temperature instability (NBTI) without device performance degradation. Also, the Si capped device exhibits the better NBTI reliability than the Si channel device. Because a Si capped structure forms the double barrier layer in the interface, it is the...
Sources responsible for local and inter-die threshold voltage (Vt) variability in undoped ultra-thin FDSOI MOSFETs with a high-k/metal gate stack are experimentally discriminated for the first time. Charges in the gate dielectric and/or TiN gate workfunction fluctuations are determined as major contributors to the local Vt variability and it is found that SOI thickness (TSi) variations have a negligible...
This paper presents an innovative structure based on 3 dimensional integration technology, where ultra thin inter layer dielectric enables a dynamic threshold voltage (VTH) control. A sequential process flow is proposed to fabricate 3D devices with dynamically tunable VTH. This ability can be exploited to design SRAMs cells with increased stability and surface density compared to planar technology...
Plasma-exposed Si surface related to Si recess in source/drain region was investigated in detail for various superposed bias configurations with frequencies of 13.56 MHz and 400 kHz. Two different bias powers were utilized by an inductively coupled plasma reactor (ICP). The surface layer (SL) and the interfacial layer between the SL and Si substrate (IL) were analyzed by spectroscopic ellipsometry...
Sub-100 nm metal source/drain (MSD) Ge-pMOSFETs are successfully fabricated and the device performance is analyzed from the aspect of source-to-channel carrier injection properties. Our full-band based device simulator is able to reproduce the experimental device characteristics, revealing that the low source-to-channel injected carrier density (Ns) of MSD Ge-devices could limit their source-drain...
A pFET threshold-voltage (Vt) reduction of about 200 mV is demonstrated by inserting a thin Al2O3 layer between the high-k dielectric and the TiN gate without noticeable degradation of other electrical properties. HfSiOpropcapped with 9 Aring of thin Al2O3obtains a low long-channel Vt of -0.37 V (the lowest among those with TiN gate), a high mobility of 59 cm2 /V ldr s at 0.8 MV/cm (92% of universal...
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