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The electrical characteristics and reliability of HfO2-based p-GaAs metal-oxide-semiconductor (MOS) capacitors (EOT: 2.4 nm to 4.8 nm) with a thin Silicon (Si) interfacial passivation layer (IPL) have been investigated with different thicknesses of HfO2. SILC generation kinetics and flat band instability were investigated via CVS and CCS measurements. In addition, breakdown voltages of gate oxide...
We report high performance (100) and (110) oriented single-grain TFTs below 600°C by orientation controlled μ-Czochralski process. Due to surface and in-plane orientation control, the uniformity approaches to the SOI counterpart. Electron mobilities are 732cm2/Vs for (100) and 630cm2/Vs for (110). Devices show stable performance under gate and drain stress respectively. After applying electrical stress...
Tunnel field-effect transistors (TFETs) have extremely low leakage current, exhibit excellent subthreshold swing, and are less susceptible to short-channel effects. However, TFETs do face certain special challenges, particularly with respect to the process-induced variations in the following: 1) the channel length and 2) the thickness of the silicon thin film and gate oxide. This paper, for the first...
To improve the bSPIFET, the SA-bSPIFET which used self-aligned process had been proposed. However there are many characteristics of bSPIFET not yet be studied. This paper focuses on the misalignment of gate shift (GS) in a 30 nm bSPIFET. Based on 2D simulation, the misalignment of GS will influence the electrical characteristics causing the degradation of the short channel behaviour and the stability...
A non-classical device structure namely self-aligned quasi-silicon-on-insulator (SOI) metal-oxide semiconductor (MOS) field-effect transistor with pi-shaped semiconductor conductive layer (SA-piFET) is presented, seeking to improve the performance and upgrade the reliability of the SOI-based devices. Designed to equip with a SA single crystal silicon channel layer, plus a natural source/drain (S/D)...
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