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High-Level Synthesis (HLS) has opened an opportunity for software programmers to target FPGA more rapidly. When developing HLS tools, tests are desirable to ensure their function, reliability and performance. When modifications are applied to a tool, Non- Regression Test (NRT) asserts that the changes have intended effect while Regression Test (RT) verifies that the tool still performs correctly without...
In this work a flexible converter control framework is presented for research and agile development of converter control systems. The platform is composed of a controller board and a software development framework. The control platform is distinguished by flexible pheriphals implemented in a FPGA which also contain a converter model for real-time simulation during control and software development...
Modern FPGAs often provide a number of highly optimized hard IP blocks with certain functionalities. However, manually instantiating these blocks is both time-consuming and error-prone, in particular, if only a part of the functionality of the IP block is used. To solve this problem, we developed an algorithm to automatically replace a selected combinational subset of a hardware design with a correct...
The SHA-1 algorithm in Hash Function was widely used in TPM hardware design. This paper proposes a design of SHA-1 hash function operations on FPGA hardware implementations. Optimized the structure of the module about the algorithm, which implement the simulation and synthesis. The frequency and resource used was satisfied with the TPM specification. Implement the modules use Hardware Design Language...
Many complex computational problems have to be overcome in the Computer Numerical Control (CNC) system, such as tool compensation calculation, contour interpolation, speed decomposition, position control and so on. If all the functions are accomplished by software, the corresponding execution time will affect the velocity of the CNC system. This paper has put forward a scheme of software hardening...
Logic emulators are extensively used for research and educational purpose in the field of digital systems design. Development of programmable devices enabled hardware emulation of complex digital circuits and systems. Comparing to the traditional digital model simulation, the physical implementation of the circuit on the emulator platform enables real application research. There are a lot of commercial...
A method of FPGA implementation of the class of parametric digital conjunctions defined by (p)-monotone sum of basic t-norms is proposed. The paper presents the logical diagrams of parametric digital conjunctions developed by means of VHDL language in Quartus II with ModelSim software of Altera. Parametric digital conjunctions can be used in reconfigurable digital fuzzy systems where the parameter...
The growth of fuzzy logic applications led to the need of finding efficient ways to implement them. The FPGAs (Field Programmable Gate Arrays) are reconfigurable logic devices that provide mainly practicality and portability, with low consumption of energy, high speedy of operation and large capacity of data storage. These characteristics, combined with the ability of synthesizing circuits, make FPGAs...
Most of the classifiers suffer from curse of dimensionality during classification of high dimensional image data. In this paper, we introduce a new supervised nonlinear dimensionality reduction (S-NLDR) algorithm called evolutionary strategy based supervised dimensionality reduction (ESSDR). The ESSDR method uses population based evolutionary strategy (ES) algorithm to find low dimensional embedded...
Radiation tolerance can be achieved by triplicating all the circuits and using majority voting, triple module redundancy (TMR), to remove faults caused by radiation. This approach, applied blindly, requires at least a 3?? increase in hardware and power consumption. In this paper we introduce an automated low cost software platform for efficiently performing fault injection experiments targeting single...
A semi-formal verification technique, which performs a brute-force compiled simulation with a sophisticated search space pruning, has been proposed and shown to be competitive with the state-of-the-art SAT-based verification techniques. This paper presents a novel approach for accelerating the semi-formal verification by utilizing hardware/software co-execution. To maximize the gain from hardware...
Traditional evolutionary algorithms require a lot of memory and processing power on embedded logic projects. Representing populations of candidate solutions through vectors of probabilities rather than sets of bit strings saves memory and processing. The concise evolutionary algorithm (CEA) is a probability vector based evolutionary algorithm. The article presents an FPEA realization of the standard...
The design based on ARM techniques is to realize a common model of communication equipment simulator. The S3C2410 chip, as the core of hardware, together with FPGA and other interface circuits, realize standardized coding and display controlling; the backstage computer software as a finite-state machine, need to give correct operating response, send display orders, communicate with other simulator...
Early detection of side channel leakage in the design of a digital crypto circuit is as important as getting the design functionally correct. Currently, side channel leakage is confirmed by measuring actual prototypes, or by detailed SPICE level simulations of the hardware model. However, this feedback does not help the designer: it comes either too late (after the implementation), or else it has...
Todaypsilas verification challenges require high-performance simulation solutions, such as hardware simulation accelerators and emulators, that have been in use in hardware and electronic system design centers for approximately the last decade. In particular, in order to accelerate functional simulation, hardware emulation is used so as to offload calculation-intensive tasks from the software simulator...
The diagnosis of infection caused by E.Coli seems to be one of the primary pre-requisites of successful medical treatment and as such is a high priority in clinical science for the diseases like Urinary Tract Infections and Sepsis. Researchers have proved that diagnosis of microbial infections can be improved by E-sniffer technology which consists of Artificial Neural Network as pattern recognizer...
Reconfigurable computing is being used to achieve high speed of application specific integrated circuits (ASICs), on the one hand, and the flexibility of the general purpose processors (GPPs), on the other. However, due to the requirement of multiple reconfigurations to complete a computation, the reconfiguration overhead might degrade the performance of the system. In order to avoid excessive reconfiguration,...
This paper describes a hardware implementation of an ATM Adaptation Layer (AAL) type 2 receiver. The simulation performance of the developed prototype is measured with real AAL type 2 encoded material and compared to two software-based AAL type 2 receiver implementations. The advantages and disadvantages of hardware-based and software-based simulation approaches in product development and prototyping...
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