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Random Telegraph Noise (RTN) has become dominant with transistor rapid scaling in recent years. We simulate RTN-induced frequency fluctuation of Ring Oscillators (ROs) using a circuit-level simulator to replicate measurement results from previous works. Consequently, we can predict dependences of frequency fluctuation on operating voltages, number of ROs stages, gate widths, and body biases.
This article presents a variability resilient CNFET based 10T S RAM cell. Critical design metrics of S RAM cells are estimated using Monte-Carlo simulations and compared with that of conventional Si-MOSFET based 10T S RAM cell. The CNFET based SRAM cell offers 3.15× and 1.98× improvements in Read Access Time (TRA) and Write Access Time (TWA) respectively. The proposed bit cell also offers 1.94× and...
Crosstalk noise is a critical issue in the deep submicron circuit design, since it causes functional failures in IC chips. This paper proposes an efficient approach to find the timing region of the circuit that timing failure occurs in an IC chip. The proposed method efficiently finds timing failure region by using CGOV metric without iterative simulations. In the experimental results, the proposed...
This work is intended to provide a set of guidelines for the design of digital-to-analog converters enabling the reduction of threshold dispersion in multichannel readout circuits for radiation detectors. The design criteria are first established through a theoretical approach and then confirmed by means of a simulation tool based on Monte Carlo methods. This latter tool provides a fast and flexible...
A new SRAM design is proposed. Body biasing improves the static noise margin (SNM) improved by at least 15% compared to the standard cells. Through using this technique, lowering supply voltage is possible. This SRAM cell is working under 0.3 V supply voltage offering a SNM improvement of 22% for the read cycle. Write Margin is not affected due to using body biasing technique. 65 nm ST models are...
We study the impact of statistical leakage modeling on the yield of memory designs. We critically evaluate different closed form models from a rare fail event perspective and propose CDF matching as a comprehensive and effective approach for accurate statistical leakage modeling. While Schwartz-Yeh method is found to match the body and left tail of the distribution, the Fenton-Wilkinson method aims...
This paper discusses the implications of noises in a pulse-density modulation single-electron circuit based on vestibulo-ocular reflex model. The proposed circuit consists of an ensemble of single-electron integrate-and-fire neurons that encode the input voltage into pulses whose temporal density is proportional to the amplitude of the input. We confirmed that static noises (heterogeneity in circuit...
Simultaneous switching noise (SSN) is an important issue for the design and test and actual ICs. In particular, SSN that originates from the internal logic circuitry becomes a serious problem as the speed and density of the internal circuit increase. In this paper, an on-chip monitor is proposed to detect potential logic errors in digital circuits due to the presence of SSN. This monitor checks the...
The paper presents a detailed study on the idle leakage reduction techniques on partially depleted silicon-on-insulator (PD-SOI) CMOS SRAM. The most promising leakage reduction techniques that have been proposed are introduced, analyzed and compared into 65 nm low-power PD-SOI technology, taking into account all the SOI specific effect. Especially, it is shown that the leakage reduction techniques...
In this work, the bulk-gate controlled circuit to improve the power supply ripple ratio (PSRR) of a Low Dropout Regulator (LDO) which deteriorates due to lowering power consumption is proposed. Designing with 0.25 mum CMOS process, the simulation results by HSPICE shown that the proposed circuit provides a high performance of PSRR even though 1/10 of the power consumption is reduced compare to the...
Data retention power gating is a commonly used method for leakage reduction in deep submicron SRAM. However, application of such methods result into reduced stability of the SRAM bitcell. Moreover, reducing supply voltage and increasing process variation put a limitation on such usage in deep submicron processes. Present scheme describes a method to enhance stability while applying such data retention...
For several decades, the output from semiconductor manufacturers has been high volume products with process optimisation being continued throughout the lifetime of the product to ensure a satisfactory yield. However, product lifetimes are continually shrinking to keep pace with market demands. Furthermore there is an increase in dasiafoundrypsila business where product volumes are low; consequently...
This paper compares readout powers and operating frequencies among dual-port SRAMs: an 8T SRAM, 10T single-end SRAM, and 10T differential SRAM. The conventional 8T SRAM has the least transistor count, and is the most area efficient. However, the readout power becomes large and the cycle time increases due to peripheral circuits. The 10T single-end SRAM is our proposed SRAM, in which a dedicated inverter...
This paper presents an innovative structure based on 3 dimensional integration technology, where ultra thin inter layer dielectric enables a dynamic threshold voltage (VTH) control. A sequential process flow is proposed to fabricate 3D devices with dynamically tunable VTH. This ability can be exploited to design SRAMs cells with increased stability and surface density compared to planar technology...
Novel 3D stacked gate-all-around multichannel CMOS architectures were developed to propose low leakage solutions and new design opportunities for sub-32 nm nodes. Those architectures offer specific advantages compared to other planar or non planar CMOS devices. In particular, ultra-low IOFF (< 20 pA/mum) and high ION (> 2.2 mA/mum) were demonstrated. Moreover, those transistors do not suffer...
A high intercept points, cost-effective, and power-efficient switching FET double balanced mixer (DBM) is reported. The Switching FET DBM demonstrated in this work offers input intercept points (IIP3) and conversion loss typically 44 dBm and 8.5 dB respectively with 15 dBm LO power for the frequency band (RF: 900-2150 MHz, LO: 850-1950 MHz, IF: 50-200 MHz). The measured interport isolation is typically...
In deep submicron era, to prevent larger amount of SRAM from more frequently encountered overheating problems and react accordingly for each possible hotspots, multiple ideal run-time temperature sensors must be closely located and response rapidly to secure system reliability while maintaining core frequency. This paper presented a method to extract run-time temperature information from multiple...
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