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Engineering change orders (ECOs), which are used to apply late-stage specification changes and bug fixes, have become an important part of the field-programmable gate array design flow. ECOs are beneficial since they are applied directly to a placed-and-routed netlist which preserves most of the engineering effort invested previously. Unfortunately, designers often apply ECOs in a manual fashion which...
This paper deals with the fault propagation and reliability of large-scale circuit and attempts to provide effective information for fault diagnosing. We analyse sample circuits from IBM benchmark suit by constructing directional weighting networks and modeling fault propagation. Roles of circuit network parameters are investigated and reliability analysis is given. The result from this work clearly...
Complexity of design and the lack of suitable test methodology are the major obstacles for widespread use of asynchronous circuit in digital circuit design. Template based synthesis of asynchronous circuits is accepted as an effective way to decrease the complexity of design. However, test frameworks such as fault simulator for synchronous circuits are not applicable for template based asynchronous...
This paper demonstrates the low energy operation of 4-bit ripple carry adder (RCA) employing two phase clocked adiabatic static CMOS logic (2PASCL) circuit techniques. We evaluate NOT, NAND, XOR and NOR logic gates on the basis of the 2PASCL topology using SPICE implemented using 0.18 ??m CTX CMOS technology. For NOT circuit, analytical and simulation values are compared. By removing the diode from...
Hybrid CMOS-SET architectures, which combine the merits of CMOS and SET (single-electron tunneling) devices, promise to be a practical implementation for nanometer-scale circuit design. In this work we propose two binary full adders using hybrid CMOS-SET parallel architectures, which take advantage of the Coulomb oscillation with SET devices in order to improve the circuit area, power consumption...
When physically implemented, independent component analysis (ICA) algorithm can achieve a real time blind signal separation (BSS). However, due to the limited size of the hardware device in microelectronics technology, several constraints can be encountered to reach the real time processing since the application of the ICA algorithm requires the consumption of a huge number of input signal samples...
Mixed-Signal extensions to VHDL, Verilog, and SystemC languages have been developed in order to provide a unifying environment for the modeling and verification of Analog and Mixed Signal (AMS) designs at different levels of abstraction. In this paper, we model the behavior of a set of benchmark designs in VHDL-AMS, Verilog-AMS and SystemC-AMS and compare the simulation performance with HSPICE. The...
CDM protection techniques for two important circuits are developed. In the first protection dummy logic circuits are added for separated small power domains. The dummy logic circuit can assist parallel-connected ESD protection devices to discharge CDM current at the initial discharge phase of the CDM event. The second protection technique for input gate protection is to use the stack-structured input...
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