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This paper presents a CMOS low-dropout regulator (LDO) with a unique power supply rejection (PSR) boosting technique. A replica device is used to cancel the power supply noise at the output that is coupled through the main LDO parasitic. The proposed LDO employs a mid-ranged output decoupling capacitor of 50nF and a comparatively low-complexity circuitry to achieve the supply rejection target while...
This paper presents a 0.65-V flipped voltage follower (FVF)-based regulator with an embedded sub-1-V voltage reference. A low-pass filter is employed in the current coupling path to reduce the bias noise and improve the power supply rejection (PSR) at a low-frequency band (<kHz). The chip is fabricated in a 0.18-μm CMOS process and occupies an active area of 0.076 mm2. The proposed FVF regulator...
The paths for power supply noise leakage in low drop-out (LDO) voltage regulators are analyzed, and techniques are discussed to minimize their effects on the output voltage. An internally compensated high power supply rejection (PSR) LDO voltage regulator with adaptive supply noise compensation scheme is presented. Its regulated output voltage is 1.6 V to provide 0–50 mA of current with a power supply...
This paper presents design techniques for a high power supply rejection (PSR) low drop-out (LDO) regulator. A bulky external capacitor is avoided to make the LDO suitable for system-on-chip (SoC) applications while maintaining the capability to reduce high-frequency supply noise. The paths of the power supply noise to the LDO output are analyzed, and a power supply noise cancellation circuit is developed...
Combining the supply ripple subtraction and high-pass filtering can improve the power supply rejection (PSR) over wideband frequency of low dropout regulator (LDO). The proposed LDO is fabricated by TSMC 0.35 ??m 2-poly 4-metal CMOS process. The simulation results at maximum load current of 100 mA, show that PSR at 10 k, 100 k and 1 M are -72 dB, -75 dB and -46 dB, respectively. Therefore, it's well...
This document presents a compilation of results from tests performed by iRoC Technologies on SER induced by alpha particles on SRAM memories for technology nodes from 180 nm to 65 nm. The aim of this study is to establish the variation of sensitivity with technology node for SEU and MCU, and to analyze the possible influence of different designs and technological parameters at a given technology node.
An on-chip buck converter with 3D chip stacking is proposed and the operation is experimentally verified. The manufactured converter achieves a maximum power efficiency of 62% for an output current of 70mA with a switching frequency of 200MHz and a 2x2mm on-chip LC output filter in 0.35mum CMOS. The use of glass epoxy interposer to increase the maximum power efficiency up to 71.3%, and the power efficiency...
In this work, the bulk-gate controlled circuit to improve the power supply ripple ratio (PSRR) of a Low Dropout Regulator (LDO) which deteriorates due to lowering power consumption is proposed. Designing with 0.25 mum CMOS process, the simulation results by HSPICE shown that the proposed circuit provides a high performance of PSRR even though 1/10 of the power consumption is reduced compare to the...
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