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The main building blocks used in digital signal processing and multimedia applications are the adders and multipliers. Better the performance of adder structure better will be the performance of multipliers in total aspect. Reducing power dissipation, delay and area at the circuit level is considered as one of the major factors in developing low power systems. In this we present different topologies...
The trade-off between speed and power consumption has become a critical concern as process technology make in-roads to 40nm proximity in modern VLSI technology. We can reduce this trade-off by compensating with accuracy i.e. if an application like Digital signal processing (DSP) can accept some errors then a large power can be saved and at the same time speed can be enhanced. In this paper, we propose...
Various physical layer protocols are employed to encode information bits in short range wireless communication technologies. In this paper, we propose a multimode hardware architecture for a digital baseband encoder which incorporates Manchester, Differential Manchester and FM0 codes. These codes help in achieving good DC balance thereby improving signal reliability. Alternating Manchester with Differential...
This paper comprises of new low power multiplication algorithm and VLSI architecture. The one less than previous is foundation to built the proposed algorithm. The algorithm is simple straightforward to find NxN unsigned binary number multiplication using 2n-1 constant number which is used recursively for both multiplicand and multiplier. It revealed that reusability of the hardware resource results...
In this paper we propose a new architecture for an efficient MAC (Multiplier Accumulator Unit) unit with low area consumption which includes Vedic Square as an alternate component in the MAC unit. Vedic Square is based on the principle of Duplex property of Urdhva Tiryagbhya. Using the proposed architecture, 50% of logic gates are reduced from the basic level of 2*2 bit and 12.64% from 16*16 bit square...
Carry select adder (CSLA) is one of the fastest adders used in many data processing systems. By eliminating the redundant logic operations in the conventional CSLA the area and power can be reduced. Logic optimization is done by providing a separate carry generator for final carry bit of each block in the SQRT CSLA. Using this logic optimization technique an area and power efficient architecture is...
Subrange ADC with Dynamic Architecture and Frequency Scaling(DAFS) is presented, which has exponential power scaling against frequency with high-speed operation of over 1GS/s. We propose Live Configuring Technique(LCT) to adaptively configure the sub-ADC operation between binary-search and flash every clock cycle, reflecting the conversion delay. The power consumption is cut down significantly and...
This paper presents a reduced-complexity low power error-resilient K-Best MIMO Detector. A novel tree-enumeration method is proposed such that the error-resilient detection processes a reduced search space and is more suitable for VLSI design. Moreover, a circuit-level optimization is employed to further simplify the complexity. Experimental results are given showing that the circuit-level optimization...
This work evaluates the performance of Neuromorphic architecture for accessing Static Random Access Memory (SRAM) in an asynchronous manner. Spike-Timing Dependent Plasticity (STDP) learning algorithm for updating the synaptic weights values in the SRAM module. Input, output, and synaptic weight values are transmitted to/from the chip using a common communication protocol based on the Address Event...
Due to the increased demand of SRAM with large use of SRAM in System On-Chip, the oxide thickness has become a tough challenge in CMOS technology. The leakage power also affects the chip design process. Speed of SRAM and Power consumption are also taken care of for designing a chip. This article represents the simulation of 6T SRAM; Asymmetric SRAM cells using low power reduction techniques. All the...
The key problems in designing of VLSI circuits are high power consumption, larger area utilization and delay which affect the speed of the computation and also results in power dissipation. In general speed and power are the essential factors in VLSI design. For solving the issues, a new architecture has been proposed. In the proposed system, the two high speed multipliers, Modified booth multiplier...
Carry Select Adder (CSLA) is one of the fastest adders used in many data-processing processors to perform fast arithmetic functions. From the structure of the CSLA, it is clear that there is scope for reducing the area and power consumption in the CSLA. This work uses a simple and efficient transistorlevel modification in BEC-1 converter to significantly reduce the area and power of the CSLA. Based...
In this paper, we have proposed a write efficient SRAM cell. The write power consumption is reduced compare to the 6T cell due to two extra nMOS tail transistors in the pulldown path of the respective inverter. These two tail transistors avoid the discharging of bitlines. The proposed cell is simulated with the help of the MICROWIND3 using advanced BSIM4 model. The SRAM cell is 1.85X faster and consumes...
This paper proposes a high-throughput cost-effective and low-power implementation of AES (Advanced Encryption Standard) supporting encryption and decryption with 128-bit cipher key. Considering the cost-effective and low-power, resource-sharing scheme is employed to reduce the hardware complexity of the cipher and decipher. In addition, we adopt composite field arithmetic solution to implement SubByte/InvSubByte...
This paper describes the architecture and VLSI (very large scale integration) implementation of a direct digital frequency synthesizer (DDFS) based on a hybrid CORDIC (COordinate Rotation DIgital Computer) algorithm. It is shown that the architecture can be implemented as a multiplier-less, small ROM ( 4 times 16 -bit) and pipelined data path. A SoC (system on chip) has been designed with 0.18 mum...
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