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The realization of IoT in real world without sensing devices is impossible. These sensing devices are battery operated and energy constrained in terms of computation and communication. The optimized communication leads to longer network life time. Minimum hop count, increased connectivity and scalability are challenging issues that can be effectively addressed by clustering mechanism. In the two tier...
The paper is about the problem of reducing the power consumption in Video Distribution Networks (VDNs) under the condition of best performance provision in terms of Quality of Experience (QoE) measured at the end user. Related to this, it has been observed that, given an end-to-end video distribution network, it is the last networking segment ending to terminal that has the dominant role in the provision...
In this paper we propose to give an overview of fine-grain design techniques we demontrated past years in our lab for power reduction in complex SoCs. Those works are based on Globally Asynchronous and Locally Synchronous systems in which each IP is an independent voltage and frequency domain. After having proposed some simple DFS architectures based on GALS architectures in 130nm technology, we extended...
Due to the ever-increasing demands on energy efficiency, designers are struggling to construct efficient and correct power management strategies for complex System-on- Chips (SoCs). The validation of an efficient power intent for a SoC is challenging and should be considered at early stage of the electronic system-level (ESL) design flow. To tackle this issue, we propose a high-level modeling approach...
The AMchip is a VLSI device that implements the Associative Memory function, a special content addressable memory specifically designed for high energy physics applications and first used in the CDF experiment at Tevatron. The 4th generation of AMchip has been developed for the core pattern recognition stage of the Fast TracKer (FTK) processor: a hardware processor for online reconstruction of particle...
In this paper, we address the problem of an efficient mapping of intellectual property (IP) cores onto a multiprocessor system-on-chip (MPSoC). The MPSoC is statically scalable in terms of number of IP cores and an 1-ary n-mesh network-on-chip (NoC). The approach places more affine IP cores closer to each other and affinity is based on an amount of exchanged communication and administration data....
Content-Centric Networking (CCN) is a recently proposed networking architecture that can potentially lead to reduced bandwidth usage and better scalability and security as compared to the current IP-based architecture. In this paper, we conduct an energy consumption analysis of content-centric networking and IP-based networking for a video streaming scenario. We consider two types of energy consumption:...
Mobile and wireless communication has been evolved from the basic model for providing point-to-point (PtP) voice centric services into more complicated service provision technologies with point-to- multipoint (PtM) transmission mode, such as MBMS in 3GPP and BCMCS in 3GPP2. On the other hand, the evolution of mobile and wireless communication has also resulted in a large number of wireless technologies...
Base Stations (BSs) cooperation techniques, also referred to as Coordinated Multi-Point (CoMP) in the 3GPP terminology, promise significant performance gains in future 4G and beyond systems. The counterpart to such gains is represented by the challenging requirements that CoMP puts on the backhaul network, which may prevent the inclusion of certain BSs selected for the cooperative cluster. The consequences...
Energy efficiency is becoming an increasingly important factor to consider in day-to-day operations, and the Information, Communication and Technology (ICT) arena is no exception. The energy consumption in the ICT sector is increasing at a rate that deems energy consumption a possible limitation to the continuous fast growth of the future Internet. We address this limitation in two ways. (1) We propose...
Networks on Chip have been proposed as a solution to mitigate complex on-chip communication problems. NoCs are composed of intellectual properties which are interconnected by on-chip switching fabrics. A step in the design process of NoCs is hardware virtualization which is mapping the IP cores on to the tiles of a chip. The communication among the IP cores greatly affects the performance and power...
With the rapid development of the Internet applications and the explosion of end users, IP address has been exhausted and routing lookup speed is the bottleneck of router design. In addition TCAM is widely used for implementation fast IP forwarding table lookup. However, the need to maintain a sorted list incremental updates may slow the lookup speed in a TCAM. In this paper, a fast TCAM update scheme...
High throughput chip-level integration of communicating heterogeneous elements (CLICHE) architecture to achieve high performance networks on chip (NoC) is proposed. The architecture increases the throughput of the network by 40% while preserving the average latency. The area of high throughput CLICHE?? switch is decreased by 18% as compared to CLICHE?? switch. The total metal resources required to...
In this paper, we present a minimum-path mapping algorithm based on genetic algorithm that automatically maps IP cores onto 2D mesh network on chip (NoC) architecture. Our algorithm consists of node mapping and minimum routing paths selection. These steps map core communication graphs onto 2D mesh NoC architectures for optimizing communication power consumption and balancing the traffic across the...
With growing integration, power consumption is becoming a challenging issue for mobile systems. Todaypsilas complex SoCs integrate advanced power management strategies, at both HW and SW level. HW mechanisms such as clock gating, power switches or voltage and frequency scaling optimize dynamically the power profile. In such architectures, power estimation at application level is a major concern for...
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