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A proposed phase-interpolator (PI) based hybrid digital pulse width modulator (DPWM) effectively resolves the trade-off between resolution and power consumption. Conventional DPWM delay-line-based architectures suffer from high power consumption limited delay time per delay-tap due to process technology, while the proposed solution replaces the delay line with a PI featuring sub-gate-delay resolution...
In this paper, implementation of an energy-efficient, low power, noise immune 4×4 Vedic Multiplier is proposed. The adder circuit used as building block in the multiplier unit is designed using semi-domino logic. The proposed multiplier unit has its benefits in terms of power consumption, delay, Energy-Delay-Product and UNG. This circuit exhibits a lower EDP of 2.88 Tena Micro to 27.97 Tena Micro,...
As the technology scales toward deeper submicron, system-on-chip designs have migrated from fairly simple single processor and memory designs to relatively complicated systems with higher communication requirements. Network-on-chip architectures emerged as promising solutions for future system-on-chip communication architecture designs. However, the switching and routing algorithm design of network-on-chip...
This paper reports on a content addressable memory (CAM) employing a multi-Vdd scheme for low power pattern recognition applications. The complete design, simulation and testing of the chip is presented along with an exploration of the multi-Vdd design space. The proposed design, operating at an optimal operating point in a triple-Vdd configuration, increases the delay range by 2.4 times and consumes...
This paper presents a low power AES-GCM authenticated encryption IP core which combines an improved four-parallel architecture, an advanced 65nm SOTB CMOS technology and a low complexity clock gating technique. As a result, the power consumption of the proposed AES-GCM core is only 8.9mW which is lower than other AES-GCM IP cores presented in literature. The detail implementation results are also...
Significant challenges imposed on the design and optimization of clock-dependent systems have re-sparked interest in alternative circuit design approaches. Null Convention Logic, a quasi-delay-insensitive asynchronous design paradigm has gained significant support recently due to its intuitive circuit design and optimization approaches as well as its readiness for design automation. Just as for synchronous...
Seeking low-power consumption high-performance embedded systems has been at the center of interest for researchers around the world for the last decades, especially with the recent boom of different hand-held battery-operated mobile connected devices. The new trends and needs of faster, smarter and smaller internet connected systems, also known as the IoT, require developing very-low power embedded...
Carry Select Adder (CSA) is faster than any other adders used in many data-processing processors to achieve arithmetic functions speedily. By observing the structure of the CSA, it is clear that there is way for reducing the delay and power consumption. This work uses a sophisticated and efficient gate-level modification to significantly reduce the delay and power of the carry select adder. From the...
4×4 Vedic multiplier using domino logic is proposed in this paper. The designs are implemented in GPDK 90nm technology on cadence virtuoso tool using spectre simulator. Multiplication is a fundamental operation, which is widely used in many digital signal processing systems, multimedia applications, computers and many digital systems. Power and delay are two important design constraints but there...
This paper presents a high-speed energy-efficient analog-to-digital converter (ADC) with two-channel time-interleaving on an asynchronous pipelined-flash architecture for each channel. With use of multiple sampling paths as well as asynchronous control by a low-power 6-phase clock generation, the proposed ADC eliminates power-hungry and bandwidth-limited residue amplifiers without sacrificing the...
Designers of complex SoCs have to face the issue of tuning their design to achieve low power consumption without compromising performance. A set of complementary techniques at hardware level are able to reduce power consumption but most of these techniques impact system performance and behavior. At register transfer level, low power design flows are available. Unfortunately, equivalent design flows...
High Efficiency Video Coding (HEVC) in-loop filtering includes the deblocking filter (DF) and the sample adaptive offset filter which consume about 20% of the total HEVC de coding time. In this paper a very energy efficient programmable multicore coprocessor for HEVC in-loop filtering is proposed. The coprosessor is placed and routed using leading edge 28nm technology to show that it can be clocked...
In this paper, Fixed-width Reduced Precision Replica Redundancy Block (RPR) design is adopted in Algorithmic Noise Tolerant (ANT) architecture. The main objective of this design is to achieve High Precision, Low power and high speed multiplier. By using Fixed-width RPR computation error can be identified and corrected. The ANT architecture was implemented using Xilinx and ModelSim tool. Performance...
Various physical layer protocols are employed to encode information bits in short range wireless communication technologies. In this paper, we propose a multimode hardware architecture for a digital baseband encoder which incorporates Manchester, Differential Manchester and FM0 codes. These codes help in achieving good DC balance thereby improving signal reliability. Alternating Manchester with Differential...
The growing complexity of systems-on-chip creates the need to replace the bus-based architecture. Network-on-chip has been proposed to address the communication bottleneck of system-on-chip. Router is the key component of network-on-chip architecture. Router frequency is one of the critical parameters, which has direct impact on network-on-chip performance. This paper proposes an adaptive scheme for...
Recent high performance computing (HPC) systems and supercomputers are built under strict power budgets and the limitation will be even severer. Thus power control is becoming more important, especially on the systems with accelerators such as GPUs, whose power consumption changes largely according to the characteristics of application programs. In this paper, we propose an efficient power capping...
In this paper, optimizations for asymmetric Network-on-Chip (NoC) router architectures are proposed for heterogeneous 3D-System-on-Chips (SoCs). The optimizations cover buffer reorganization among dies and focus on power and area savings. The architectures are compared to conventional, symmetric routers on the bases of synthesizable RTL models. Area savings of 8.3% and power savings of 5.4% for link...
The main challenge for a design engineer is not only to design a successful SoC with a well-structured and synthesizable RTL code but also to design it with efficient in energy and optimized in power consumption. The aim of the paper is to implement AMBA APB (advanced microcontroller bus architecture — advanced peripheral bus) Bridge with efficient deployment of system resources. For this, simulation...
A low-power hybrid analog-to-digital converter (ADC) architecture for high-speed medium-resolution applications is introduced. The architecture is a subranging time-interleaved ADC. In the first stage, a fast flash ADC resolves the three most significant bits. The remaining bits are generated by four time-interleaved low-power successive approximation register (SAR) ADCs, leading to 8-bit 1GS/s operation...
This paper presents the hardware implementation of the Linear Feedback Shift Register (LFSR) based Substitution Box (S-Box) using ALTERA FPGA platform. Unlike the conventional designs, the proposed architecture is low in terms of its hardware cost; the total area and power consumptions. Hence, the new LFSR based S-box can be deployed in block ciphers to achieve lightweight cryptographic implementations.
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