The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
With the exponentially increasing capacity demands anticipated in next generation wireless networks, densifying the network using cmW and mmW small cells supporting high bandwidths is seen to be the trend in 5G networks. Such ultra-dense deployment of cells would also lead to a higher amount of power consumption, from the UE and network perspective, due to the increased measurement requirements and...
Small Cells are under extensive investigation as a potential solution to meet the increasing capacity demand due to ever growing data traffic over cellular networks. The architecture of small cells is still under discussion, various architectures have been proposed based on potential use cases. One of the most important use cases is to deploy small cells on a different frequency than that of the macro...
An 8-core SPARC64™ VIIIfx processor is fabricated in a 45nm CMOS process and achieves a peak performance of 128GFLOPS. Measured results show that the processor consumes only 58W of power when executing a maximum power program. Fine-grained power analysis was used to tune the micro-architecture for low power consumption, and circuit-level low-power techniques were developed. Water cooling and supply...
While the CMOS analog circuits can be designed with the minimum-gate-length of the fabrication process in the alpha-power law MOSFET model, the length of a MOSFET gate has been chosen to be a larger scale than the minimum-gate-length in the conventional Shockleypsilas square model. In this paper, we describe a 6-b 100 MSPS CMOS current steering digital-to-analog converter (DAC) with the alpha-power...
A low power reconfigurable DCT architecture is proposed, which can be run at three transform precision levels for different demands. Using the character of energy distribution of the DCT matrix after 2D DCT operation, we selected the best DCT bases which achieve considerable power reduction in DCT operation with minimum image quality degradation. The reconfigurable architecture can achieve power saving...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.