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Modern cloud storage requires a high throughput and low latency data protection system, which is usually implemented with an Advanced Encryption Standard (AES) hardware accelerator connected with CPU through PCI Express (PCIe). However, most existing systems cannot simultaneously achieve high throughput and low latency, as they impose conflicting requirements to the block size of packets used in PCIe...
Matrix operations are required in many complex algorithms in digital, image and video processing applications. The conventional method is usually used to implement matrix multiplications for small matrices. However, with the development of VLSI technology and FPGAs, there is an increasing demand for developing a high speed, low power and low area matrix multiplication system for large matrices. The...
Space communication systems are characterized by the severe limitations to the on-board computational power and the tight constraints of received signal strengths. Also, these systems observe degradation in signals caused by large propagation latencies, extreme distances traveled, as well as data corruption causing high biterror rates. LDPC codes provide powerful error correction capability where...
The security hash algorithm 512 (SHA-512), which is used to verify the integrity of a message, involves computation iterations on data. The huge computation delay generated in that iteration limits the entire throughput of the system, and makes it difficult to pipeline the computation. To shorten the computation time in an iteration of the main loop, we used the data forwarding method. Here we introduce...
Monte Carlo simulations and other scientific applications that depend on random numbers are increasingly implemented in parallel configurations in programmable hardware. High-quality pseudo-random number generators (PRNGs), such as the Mersenne Twister, are based on binary linear recurrence equations. They have extremely long periods (more than 21024 numbers generated before the entire sequence repeats)...
This paper describes 3-stage and 4-stage pipeline MD5 implementations on FPGA. This work removes the data dependency of a single step inside the main loop of the MD5 algorithm by data forwarding methodology, and breaks that single step computation into 3/4 pipeline stages. Three implementations on Xilinx Vertex-II are given with the throughput get to 1.04 Gbps, and occupy 1064 hardware slices. Thus,...
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