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This paper presents a compact control loop and a digitalized stepwise control method to improve area and power efficiency for digital-based clock and data recovery circuits (CDRs). By combining the frequency control loop and integral path with a digital adder, some tributary circuits are removed to save total area and power. Meanwhile, the stepwise control technique for constant system bandwidth is...
This paper describes a 1.25-Gb/s all-digital clock and data recovery (ADCDR) circuit with binary frequency acquisition which is never achieved in reference-less ADCDR systems. The proposed configuration of digital loop filter without any adder can minimize to loop latency and the recovered clock jitter. The proposed ADCDR circuit occupies a chip area of 0.9times0.7 mm2 and consumes 80 mW from a single...
A delay-locked loop of multi-band selector with wide-locking range and low power dissipation is presented. The architecture of the proposed delay-locked loop consists of phase frequency detector, charge pump, band selector, multi-control delay line, and start-up circuit. The multi-band selector is used to extend operation frequency of delay-locked loop by switching the multi-control delay line. The...
Timing-error detection and recovery circuits are implemented in a 65 nm resilient circuit test-chip to eliminate the clock frequency guardband from dynamic supply voltage (VCC) and temperature variations as well as to exploit path-activation probabilities for maximizing throughput. Two error-detection sequential (EDS) circuits are introduced to preserve the timing-error detection capability of previous...
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