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This work targets the miniaturization of bidirectional isolated dc-dc converters for renewable energy applications with integrated energy storage. A power IC was fabricated in a 0.18μm 80V BCD process to integrate the primary-side low-voltage bridge in Dual-Active-Bridge (DAB) converter. The targeted power level of the converter is 50 W per IC, with a high switching frequency of 1 MHz. A Phase-Locked-Loop...
Digital isolators are widely used in isolated power converters for transmitting high-frequency gating pulses. Opto-isolators generally suffer from low reliability, while emerging RF based isolators are expensive and power-hungry. In this work, two Phase-Locked-Loop (PLL) based synchronization schemes are introduced and demonstrated to operate a bidirectional Dual-Active-Bridge (DAB) dc-dc converter...
This paper describes the clock distribution and synchronization network for a 64 bit ARMv8 8-core microprocessor. Embedded in a SoC for cloud computing platforms, the processor is fabricated in a 40 nm CMOS technology and operates at 3.0 GHz. The system PLL has a measured rms jitter 1 ps and features dynamic frequency hopping for DVFS applications. In conjunction with a Star/H/Mesh topology, the...
This paper presents a Cartesian network of CMOS oscillators distributed on a chip and synchronized by a network of all-digital PLLs in phase and in frequency. Such a network may be used for generation of a global clock in large digital systems on chip. The originality of the work is in the use of a solution essentially based on digital circuits. This offers many opportunities for implementation of...
The paper presents a high-speed serial interface between external tester and Embedded Deterministic Test (EDT) compression logic hosted by SoC designs. With only a single bidirectional link, the system is capable of feeding distributed heterogeneous cores with hundreds of test channels. Moreover, it synergistically supports EDT bandwidth management to improve the overall test performance. A detailed...
Advanced high-speed source-synchronous systems such as GDDR5 use multiple source-synchronous clocks to increase memory bandwidth. Therefore, well-defined phase relationships among multiple clocks are required to perform correct read/write operations. A GDDR5 system solves this problem by adaptive clock synchronization training. For such multiple clocks synchronization training at controller side this...
This paper presents a novel architecture of on-chip clock generation employing a network of oscillators synchronized by the distributed all-digital PLLs (ADPLLs). The implemented prototype has 16 clocking domains operating synchronously in a frequency range of 1.1-2.4 GHz. The synchronization error between the neighboring clock domains is less than 60 ps. The fully digital architecture of the generation...
This fourth generation UltraSPARC T3 SoC processor (code named Rainbow Falls) implements sixteen 8-threaded SPARC cores to double on-chip thread count and throughput performance over its previous generation. It enhances glueless scalability to enable up to 512 threads in a 4-way system configuration. The 16-Bank 6MB L2 Cache, the 512GB/s hierarchical crossbar and the 312-lane SerDes I/O of 2.4Tb/s,...
This paper presents a clock control architecture for designs with multiple clock domains, and a novel mix of existing ATPG techniques as well as novel ATPG enhancements. The combination of the ATPG techniques and the clock control hardware lowers the number of test patterns in a fully automated flow, while maintaining the high coverage that is required nowadays by production test. Experimental results...
Clock distribution networks of synchronized oscillators are an alternative approach to classical tree-like clock distribution methods. Each node of the network may consist of a phase-locked loop (PLL) trying to match the phase of its neighbors. Then a network of independent oscillators takes the place of the centralized clock source, providing separate clock signals to the physically distant parts...
The Niagara2 CMT system-on-chip incorporates many design-for-test features to achieve high test coverage for both arrays and logic. All the arrays are tested using memory built-in-self-test. This is supplemented with scan-based testing. Logic is tested with standard ATPG for slow-speed defects and extensive use of transition test, along with logic built-in-self-test for the SPARC cores, for at-speed...
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