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This paper presents an efficient algorithm to detect the global topological similarity between two circuits. By applying the proposed circuit similarity algorithm in an incremental design flow, IDUCS (incremental design using circuit similarity), the design and optimization effort in the previous design iterations is automatically captured and can be used to guide the next design iteration. IDUCS...
This paper briefly describes the PhD research work on Robust FPGA Design Under Variations. The work proposes design techniques in three primary areas, viz., power yield enhancement, timing yield enhancement and IR-drop reduction. An architecture and CAD enhancement technique is proposed for improving the timing yield of FPGAs under process variations. Two different techniques are proposed for improving...
Field programmable gate arrays (FPGAs) are becoming increasingly important implementation platforms for digital circuits. This paper presents a method for symmetrical FPGA placement based on ant colony optimization (ACO). Also, we take the routing congestion into consideration by introducing a congestion factor in our algorithm. Experimental results show that compared with the state-of-the-art FPGA...
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