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With every process generation, the problem of variability in physical parameters and environmental conditions poses a great challenge to the design of fast and reliable circuits. Propagation delays which decide circuit performance are likely to suffer the most from this phenomena. While Statistical static timing analysis (SSTA) is used extensively for this purpose, it does not account for dynamic...
Noise effects due to parasitic couplings between two closely located neighboring wires have significant impact on the performance of the DSM chips. Analysis of a single wire with all its couplings is required to find out the maximum effect of the crosstalk noise both in terms of glitch and delay. This paper introduces a decoupled RLGC transient model for victim wire which is highly accurate and flexible...
This paper proposes a new formulation of black-box macromodels for electrically-long scalar interconnects, together with an efficient numerical identification scheme and an optimized SPICE synthesis. The proposed methodology explicitly preserves in the macromodel structure the infinite reflections due to termination mismatch, thus allowing for compact and low-complexity equivalent circuits. Numerical...
Based on the equivalent Elmore delay model, a new delay model that takes inductance and thermal effect into consideration is presented in this paper. The proposed model with high efficiency has closed-form expression. Its solution exhibits high accuracy as compared to the other models. Simulation results show that the error in the propagation delay is less than 10% for RLC tree example.
A notion of logic time and logic time stamp are introduced to control running order for single-period and multi-periods simulation system. Then a synchronous startup schedule strategy is designed, and its technology essential and implementation flow are discussed. According to the time stamp and the simulation logic time of interactive data, the measurement and compensation method of time-delay in...
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