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This paper proposes a novel technique to measure temperature and voltage on-chip in field test. It consists of three types of NBTI-tolerant ring oscillator and counters constructed with a standard cell library. Temperature and voltage are estimated with high accuracy and in a short time.
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This paper presents a reconfigurable, low offset, low noise and high speed dynamic clocked-comparator for medium to high resolution Analog to Digital Converters (ADCs). The proposed comparator reduces the input referred noise by half and shows a better output driving capability when compared with the previous work. The offset, noise and power consumption can be controlled by a clock delay which allows...
Delay elements are used in integrated circuits (ICs) to meet design specific timing requirements. Delays are often generated by increasing the input transition times. For long delays, such a signal generally results in prolonged short-circuit current either within the delay element itself or at the subsequent stage, elevating the overall power consumption of the system. In this paper, a novel CMOS...
This paper presents a new technique to accurately measure the data retention voltage (DRV) of large SRAM arrays in the presence of process variations. The proposed technique relies on a built-in-self-test (BIST) unit along with a DC-DC converter. The BIST unit implements a modified version of the March C- test that accounts for data retention faults. Whereas, the DC-DC converter is used to scale down...
A simple array-based test structure has been developed to characterize AC variability in deeply scaled MOSFETs. Each test structure consists of 128 devices under test (DUTs) whose relative delays are characterized using a logic gate-based delay detector circuit. The delay measurement technique only requires a single off-chip DC voltage measurement for each DUT. A design-time optimization is performed...
Excessive leakage of cache blocks encourages forcing the cache block into low-leakage state all the time except during read/write operations. By retaining the values of the cache cells during low leakage state, the penalty for re-activating the sleepy cache cells is also reduced. This is achieved using aggressive policies with simple control strategies using one of two methods. Either by adding a...
A cascadable power-on-reset (POR) delay element consuming nanowatt of peak power was developed to be used in very compact power-on-reset pulse generator (POR-PG) circuits. Operation principles and features of the POR delay element were presented in this paper. The delay element was designed, and fabricated in a 0.5 mum 2P3M CMOS process. It was determined from simulation as well as measurement results...
The objective of using logic BIST for online and periodic testing is to identify defects, like opens, resulting from the wear and tear of the circuit. We have shown that existing test sets have a low coverage for open defects located in scan flip-flops, even though such defects may affect functional operation. Existing Logic BIST structures suffer from the same limitations. A novel Logic BIST architecture...
This paper introduces a novel current sense amplifier (CSA) in sub-32nm fully depleted (FD) double-gate (DG) silicon-on-insulator (SOI) technology with planar independent self-aligned gates. A new architecture is proposed which takes advantage of the back gate in order to improve circuit properties. Compared to the reference circuit, the new architecture proves to be faster (21% sensing delay decrease),...
Continuous scaling, necessary for enhanced performance and cost reduction, has pushed existing CMOS materials much closer to their intrinsic reliability limits, forcing reliability engineers to get a better understanding of circuit failure. This requires that designers will have to be very careful with phenomena such as high current densities or voltage overshoots. In addition to the reliability issues,...
Simple ring-oscillator circuit has been used to estimate the degradation in circuit performance due to negative bias temperature instability (NBTI) effect but it fails to isolate the degradation from the NBTI for PMOS and the positive bias temperature instability (PBTI) for NMOS in high-K dielectric/metal gate CMOS technology. In this paper, we propose new circuit structures which monitor the NBTI...
A monolithic integrated comparator is presented for strobed interrogation of a difference voltage. The comparator has a dc-offset of 5 mV and provides a logic level output representing the interrogated input within 40 ns of the strobe input. Fast recovery permits operation up to 20 MHz repetition rate with a sensitivity of 20 mV. The circuit incorporates a differential amplifier stage for high common...
High-voltage MOS transistors fabricated in an ESFI-SOS technology have been investigated. Breakdown voltages exceeded 120 V. As application 100 V LCD-drivers employing dynamic bootstrap and static push-pull circuit techniques will be presented.
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